FPGA可编程逻辑器件芯片XC7Z045-2FFG676E中文规格书

Discharge Caution

CAUTION!ESD can damage electronic components when they are improperly handled, and can result in total or intermittent failures. Always follow ESD-prevention procedures when removing and replacing components.

To prevent ESD damage:

••••••

Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the equipment end of the strap toan unpainted metal surface on the chassis.

Avoid touching the adapter against your clothing. The wrist strap protects components from ESD on the bodyonly.

Handle the adapter by its bracket or edges only. Avoid touching the printed circuit board or the connectors.Put the adapter down only on an antistatic surface such as the bag supplied in your kit.

If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag immediately.If a wrist strap is not available, ground yourself by touching the metal chassis before handling the adapter or anyother part of the computer/server.

1 GB DDR3 Memory(SODIMM)FMC Connector(HPC)10/100/1000 EthernetInterfaceDifferential ClockGTP SMA ClockXADC HeaderUser Switches,Buttons, and LEDsHDMI VideoInterfaceArtix-7 FPGAXC7A200T-2FBG676CSD CardInterface128 Mb Quad SPIFlash Memory4-lane PCI ExpressEdge ConnectorLCD Display(2 line x 16 characters)1 KB EEPROM (I2C)I2C Bus SwitchDIP Switch SW1ConfigUSB-to-UART BridgeJTAG Interfacemicro-B USB ConnectorSFP+ Single CageUG952_c1_01_101512Figure 1-2:AC701 Board Block Diagram

ZC706 Evaluation Board User GuideUG954 (v1.8) August 6, 2019

Feature Descriptions

Table 1-3:I/O Voltage Rails (Cont’d)

Net Name

Voltage

QSPI0,QSPI1

VCCP1V8

1.8V

PHY_IF,SDIO_IF,USB_IFPS_DDR3_IF

XC7Z045 (U1)

Bank

PS Bank 500PS Bank 501PS Bank 502

Notes:

Connected To

1.The ZC706 evaluation board is shipped with VADJ set to 2.5V.

DDR3 SODIMM Memory (PL)

[Figure1-3, callout 2]

The memory module at J1 is a 1GB DDR3 small outline dual-inline memory module

(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM) for storing user code and data.••••

Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)Supply voltage: 1.5VDatapath width: 64 bitsData rate: Up to 1,600 MT/s

The ZC706 XC7Z045 SoC PL DDR interface performance is documented in the Zynq-7000 SoC (Z-7030, 035, 045, and Z-7100): DC and AC Switching Characteristics Data Sheet (DS191)[Ref2].

The DDR3 interface is implemented across the PL-side I/O banks. Bank 33 and bank 35 have a dedicated DCI VRP/N resistor connection. An external 0.75V reference VTTREF_SODIMM is provided for data interface banks. Any interface connected to these banks that requires the VTTREF voltage must use this FPGA voltage reference. The connections between the DDR3 memory and the SoC are listed in Table1-4.Table 1-4:

DDR3 SODIMM Socket J1 Connections to the XC7Z045 SoC

Net Name

PL_DDR3_A0PL_DDR3_A1PL_DDR3_A2PL_DDR3_A3PL_DDR3_A4PL_DDR3_A5PL_DDR3_A6

XC7Z045 (U1)

Pin

E10B9E11A9D11B6F9

I/O Standard

SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15SSTL15

DDR3 SODIMM Memory J1Pin Number

98979695929190

Pin Name

A0A1A2A3A4A5A6

ZC706 Evaluation Board User GuideUG954 (v1.8) August 6, 2019

Feature Descriptions

Configuration Source

None

Cable Connector J3(2)

Digilent USB-to-JTAG interface U30JTAG (flying lead) Header J62

DIP Switch SW4

Switch 1(1) JTAG_SEL_1

0101

Switch 2(1) JTAG_SEL_2

0011

ZC706 Evaluation Board User GuideUG954 (v1.8) August 6, 2019

Feature Descriptions

Table 1-12:ZC706 Evaluation Board Clock Sources

Clock Source

U64U37 J67(P), J68(N)

U24J36(P), J31(N)

U60

Clock Name

System ClockUser ClockUser SMA Clock

PS ClockGTX SMA REF ClockJitter Attenuated Clock

Description

SiT9102 2.5V LVDS 200MHz fixed-frequency oscillator (SiTime).See System Clock, page36.

Si570 3.3V LVDS I2C programmable oscillator, 156.250MHz default (Silicon Labs). See Programmable User Clock, page37.

User clock input SMAs, limit input swing voltage to VADJ_FPGA setting (1.8V, 2.5V, 3.3V). See User SMA Clock Source, page38.

SIT8103 1.8V single-ended CMOS 33.3333MHz fixed frequency oscillator (SiTime). See Processing System Clock Source, page39.User clock input SMAs. See GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N), page39.

Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs). See Jitter Attenuated Clock, page40.

ZC706 Evaluation Board User GuideUG954 (v1.8) August 6, 2019

Feature Descriptions

ZC706 Evaluation Board User GuideUG954 (v1.8) August 6, 2019