AT24C128

•Low-voltage and Standard-voltage Operation –2.7 (V•CC = 2.7V to 5.5V)

Internally Organized 16,384 x 8 and 32,768 x 8 •Two-wire Serial Interface

•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol •400 kHz Compatibility

•Write Protect Pin for Hardware and Software Data Protection •64-byte Page Write Mode (Partial Page Writes Allowed) •Self-timed Write Cycle (5 ms Max) •High Reliability

–Data Retention: 40 Years

•Lead-free/Halogen-free Devices Available •

8-lead JEDEC SOIC and 8-lead TSSOP

Description

The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable andprogrammable read only memory (EEPROM) organized as 16,384/32,768 words of 8bits each. The device’s cascadable feature allows up to 4 devices to share a commonTwo-wire bus. The device is optimized for use in many automotive applications wherelow power and low voltage operation are essential. The AT24C128 is available inspace-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages. The AT24C256 isavailable in a space-saving 8-lead JEDEC SOIC package. In addition, the entire familyis available in 2.7V (2.7V to 5.5V) version.Table 1. Pin Configuration

Pin Name

Function

A0 - A1Address Inputs8-lead TSSOP

SDASerial DataA018VCCSCLSerial Clock InputA127WPNC36SCLWPWrite ProtectGND45SDANCNo ConnectGND

Ground

8-lead SOIC

A018VCCA127WPNC36SCLGND45SDATwo-wire Automotive Temperature Serial EEPROMs128K (16,384 x 8)256K (32,768 x 8)AT24C128AT24C256Rev. 5121B–SEEPR–2/071

Absolute Maximum Ratings*

Operating Temperature..................................–55°C to +125°CStorage Temperature.....................................–65°C to +150°CVoltage on Any Pin

with Respect to Ground....................................–1.0V to +7.0VMaximum Operating Voltage..........................................6.25VDC Output Current........................................................5.0 mA

*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 1. Block Diagram

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Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into eachEEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collectordevices.

DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hard-wired or left not connected for hardware compatibility with other AT24CXX devices. When thepins are hardwired, as many as four 128K/256K devices may be addressed on a single bussystem (device addressing is discussed in detail under the Device Addressing section). If thepins are left floating, the A1 and A0 pins will be internally pulled down to GND if the capacitivecoupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends con-necting the address pins to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal writeoperations. When WP is connected high to VCC, all write operations to the memory are inhib-ited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitivecoupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends con-necting the pin to GND.

Memory Organization

AT24C128/256, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as256/512 pages of 64-bytes each. Random word addressing requires a 14/15-bit data wordaddress.

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Table 2. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V to +5.5V

SymbolCI/OCINNote:

Test Condition

Input/Output Capacitance (SDA)Input Capacitance (A0, A1, SCL)

1.This parameter is characterized and is not 100% tested.

Max86

UnitspFpF

ConditionsVI/O = 0VVIN = 0V

Table 3. DC Characteristics

Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V(unless otherwise noted)

SymbolVCC3ICCICCISB3ISB4ILIILOVILVIHVOL2VOL1Note:

ParameterSupply Voltage

Supply Current VCC = 5.0VSupply Current VCC = 5.0VStandby Current VCC = 2.7VStandby Current VCC = 5.0VInput Leakage CurrentOutput Leakage CurrentInput Low Level (1)Input High Level (1)

Output Low Level VCC = 3.0VOutput Low Level VCC = 1.8V

IOL = 2.1 mAIOL = 0.15 mAREAD at 100 kHzWRITE at 100 kHzVIN = VCC or VSSVIN = VCC or VSSVIN = VCC or VSSVOUT = VCC or VSS

−0.6VCC x 0.7

Test Condition

Min2.7

0.42.01.68.00.100.05Typ

Max5.51.03.04.018.03.03.0VCC x 0.3VCC + 0.50.40.2

UnitsVmAmAµAµAµAµAVVVV

SymbolVCC3ICCICCISB3ISB4ILIILOVILVIHVOL2VOL1

1.VIL min and VIH max are reference only and are not tested.

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Table 4. AC Characteristics

Applicable over recommended operating range from TA = −40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and100 pF (unless otherwise noted)

AT24C128/256

SymbolfSCLtLOWtHIGHtAAtBUFtHD.STAtSU.STAtHD.DATtSU.DATtRtFtSU.STOtDHtWR

Endurance(1)Note:

Parameter

Clock Frequency, SCLClock Pulse Width LowClock Pulse Width HighClock Low to Data Out ValidTime the bus must be free before a new transmission can start(1)Start Hold TimeStart Set-up TimeData In Hold TimeData In Set-up TimeInputs Rise Time(1)Inputs Fall Time(1)Stop Set-up TimeData Out Hold TimeWrite Cycle Time3.3V, 25°C, Page Mode

1M0.650

5

1.20.60.11.20.60.60100

3003000.9

Min

Max400

UnitskHzµsµsµsµsµsµsµsnsnsnsµsnsmsWrite Cycles

1.This parameter is ensured by characterization only.

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Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an externaldevice. Data on the SDA pin may change only during SCL low time periods (see Figure 4 onpage 7). Data changes during SCL high periods will indicate a start or stop condition asdefined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition whichmust precede any other command (see Figure 5 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After aread sequence, the stop command will place the EEPROM in a standby power mode (see Fig-ure 5 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from theEEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.

STANDBY MODE: The AT24C128/256 features a low power standby mode which is enabled:a) upon power-up and b) after the receipt of the STOP bit and the completion of any internaloperations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wirepart can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high ineach cycle while SCL is high and then (c) create a start condition as SDA is high.

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Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

SCLSDA8th BITWORDnACKtwrSTOPCONDITION(1)STARTCONDITIONNote:

1.The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Figure 4. Data Validity

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Figure 5. Start and Stop Definition

Figure 6. Output Acknowledge

Device

Addressing

The 128K/256K EEPROM requires an 8-bit device address word following a start condition toenable the chip for a read or write operation (see Figure 7 on page 10). The device addressword consists of a mandatory one, zero sequence for the first five most significant bits asshown. This is common to all two-wire EEPROM devices.

The 128K/256K uses the two device address bits A1, A0 to allow as many as four devices onthe same bus. These bits must compare to their corresponding hardwired input pins. The A1and A0 pins use an internal proprietary circuit that biases them to a logic low condition if thepins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation isinitiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is notmade, the device will return to a standby state.

DATA SECURITY: The AT24C128/256 has a hardware data protection scheme that allows theuser to write protect the whole memory when the WP pin is at VCC.

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Write

Operations

BYTE WRITE: A write operation requires two 8-bit data word addresses following the deviceaddress word and acknowledgment. Upon receipt of this address, the EEPROM will againrespond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bitdata word, the EEPROM will output a zero. The addressing device, such as a microcontroller,then must terminate the write sequence with a stop condition. At this time the EEPROM entersan internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled duringthis write cycle and the EEPROM will not respond until the write is complete (see Figure 8 onpage 10).

PAGE WRITE: The 128K/256K EEPROM is capable of 64-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not send astop condition after the first data word is clocked in. Instead, after the EEPROM acknowledgesreceipt of the first data word, the microcontroller can transmit up to 63 more data words. TheEEPROM will respond with a zero after each data word received. The microcontroller must ter-minate the page write sequence with a stop condition (see Figure 9 on page 11).

The data word address lower 6 bits are internally incremented following the receipt of eachdata word. The higher data word address bits are not incremented, retaining the memory pagerow location. When the word address, internally generated, reaches the page boundary, thefollowing byte is placed at the beginning of the same page. If more than 64 data words aretransmitted to the EEPROM, the data word address will “roll over” and previous data will beoverwritten. The address “roll over” during write is from the last byte of the current page to thefirst byte of the same page.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and theEEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending astart condition followed by the device address word. The read/write bit is representative of theoperation desired. Only if the internal write cycle has completed will the EEPROM respondwith a zero, allowing the read or write sequence to continue.

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Read

Operations

Read operations are initiated the same way as write operations with the exception that theread/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the lastaddress accessed during the last read or write operation, incremented by one. This addressstays valid between operations as long as the chip power is maintained. The address “rollover” during read is from the last byte of the last memory page, to the first byte of the firstpage.

Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. Themicrocontroller does not respond with an input zero but does generate a following stop condi-tion (see Figure 10 on page 11).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the dataword address. Once the device address word and data word address are clocked in andacknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with theread/write select bit high. The EEPROM acknowledges the device address and serially clocksout the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (see Figure 11 on page 11).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with anacknowledge. As long as the EEPROM receives an acknowledge, it will continue to incrementthe data word address and serially clock out sequential data words. When the memoryaddress limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respondwith a zero but does generate a following stop condition (see Figure 12 on page 11). Figure 7. Device Address

Figure 8. Byte Write

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Figure 9. Page Write

Notes:

(* = DON’T CARE bit)

(† = DON’T CARE bit for the 128K)

Figure 10. Current Address Read

Figure 11. Random Read

Notes:

(* = DON’T CARE bit)

(† = DON’T CARE bit for the 128K)

Figure 12. Sequential Read

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AT24C128 Ordering Information

Ordering CodeAT24C128-10TQ-2.7AT24C128N-10SQ-2.7

Package8A28S1

Operation RangeLead-free/Halogen-free/Automotive Temperature

(–40°C to 125°C)

Package Type

8S18A2

8-lead, 0.150\" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

Options

–2.7

Low-voltage (2.7V to 5.5V)

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AT24C256 Ordering Information

Ordering CodeAT24C256N-10SQ-2.7

Package8S1

Operation RangeLead-free/Halogen-free/Automotive Temperature

(–40°C to 125°C)

Package Type

8S18A2

8-lead, 0.150\" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

Options

–2.7

Low-voltage (2.7V to 5.5V)

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Packaging Information

8S1 – JEDEC SOIC

C1EE1N∅LTop ViewEnd VieweBASYMBOLCOMMON DIMENSIONS(Unit of Measure = mm)MIN1.350.100.310.174.803.815.79NOM–––––––1.27 BSC0.400˚––1.278˚MAX1.750.250.510.255.003.996.20NOTEA1AA1bCDDE1Side ViewEeL ∅Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.10/7/031150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TITLE8S1, 8-lead (0.150\" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC)DRAWING NO.8S1REV. BR14

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8A2 – TSSOP

321Pin 1 indicatorthis cornerE1EL1NLTop ViewEnd ViewCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMIN2.90NOM3.006.40 BSC4.30–0.800.194.40–1.00–0.65 BSC0.450.601.00 REF0.754.501.201.050.3043, 5MAX3.10NOTE2, 5bADEE1AeDA2A2beSide ViewLL1Notes:1.This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc.2.Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side.3.Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side.4.Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5.Dimension D and E1 to be determined at Datum Plane H.5/30/02R2325 Orchard ParkwaySan Jose, CA 95131TITLE8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)DRAWING NO.8A2REV. B15

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Revision History

Doc. Rev.5121B

Date1/2007

Comments

Implemented revision historyRemoved PDIP package offeringRemove PB’d parts

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