FPGA可编程逻辑器件芯片XCZU19EG-2FFVC1760E中文规格书

找FPGA和CPLD可编程逻辑器件，上深圳宇航军工半导体有限公司

LPDDR4 Guidelines

LPDDR4 Pin Rules

The LPDDR4 pin rules are for single and dual-rank memory interfaces.•

All unused DDR pins can be left unconnected. For example, in an -bit interfacewithout ECC, the PS_DDR_DQ to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, andPS_DDR_DM8 pins can be left unconnected.

Connect the PS_DDR_ZQ pin to GND using a 240 resistor. There should be separate240 resistors at the FPGA and at the DRAM.

To achieve maximum performance, address copy mode is suggested.

••

LPDDR4 Pin Swapping Restrictions

••••

Command/address bits cannot be swapped.

To support write DQS to DQ training, DQ byte lane swapping is not allowed.

To support write DQS to DQ training, DQ bits with bytes 0, 2, and 8 are not allowed tobe swapped.

Bits within bytes 1 and 3 can be swapped.

LPDDR4 Pinout Example for Supported Configurations

Table2-3 shows a pinout example for the LPDDR4 supported configurations. For

termination details, see the UltraScale Architecture PCB Design Guide [Ref14]. When not being used for a memory interface, all pins should be left unconnected with the exception of VCCO_PSDDR and VCC_PSDDR_PLL, which should be tied to GND.

IMPORTANT:VCC_PSINTFP must be tied to VCC_PSINTFP_DDR. This requirement is in Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics [Ref8] and Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics [Ref9], where both VCC_PSINTFP and VCC_PSINTFP_DDR must be connected to the same supply and thus both must be powered to avoid MBIST failure.

Zynq UltraScale+ Packaging and PinoutsUG1075 (v1.9) June 24, 2020

Chapter 2:PS Memory Interface Pin Guidelines

LPDDR3 Guidelines

LPDDR3 Pin Rules

The LPDDR3 pin rules are for single and dual-rank memory interfaces.•

All unused DDR pins can be left unconnected. For example, in an -bit interfacewithout ECC, the PS_DDR_DQ to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, andPS_DDR_DM8 pins can be left unconnected.

Connect the PS_DDR_ZQ pin to GND using a 240 resistor. There should be separate240 resistors at the FPGA and at the DRAM.

To achieve maximum performance, address copy mode is suggested.

••

Zynq UltraScale+ Packaging and PinoutsUG1075 (v1.9) June 24, 2020

Chapter 2:PS Memory Interface Pin Guidelines

Table 2‐4:

LPDDR3 Supported Pinout Configurations) (Cont’d)

LPDDR3 -bit

CA4_ACA5_ACA6_ACA7_ACA8_ACA9_ACA0_BCA1_BCA2_BCA3_BCA4_BCA5_B

Can be left unconnected.Can be left unconnected.CA9_B

Can be left unconnected.CA6_BCA7_BCA8_B

Can be left unconnected.CK_c_ACK_c_BCK_t_ACK_t_B

CKE_A and CKE_BCan be left unconnected.CS_n_A and CS_n_BCan be left unconnected.DM0_ADM1_ADM2_ADM3_ADM0_BDM1_B

CA4_ACA5_ACA6_ACA7_ACA8_ACA9_ACA0_BCA1_BCA2_BCA3_BCA4_BCA5_B

Can be left unconnected.Can be left unconnected.CA9_B

Can be left unconnected.CA6_BCA7_BCA8_B

Can be left unconnected.CK_c_ACK_c_BCK_t_ACK_t_B

CKE0_A and CKE0_BCKE1_A and CKE1_BCS0_n_A and CS0_n_BCS1_n_A and CS1_n_BDM0_ADM1_ADM2_ADM3_ADM0_BDM1_B

Pin Name

PS_DDR_A4PS_DDR_A5PS_DDR_A6PS_DDR_A7PS_DDR_A8PS_DDR_A9PS_DDR_A10PS_DDR_A11PS_DDR_A12PS_DDR_A13PS_DDR_A14PS_DDR_A15PS_DDR_A16PS_DDR_A17PS_DDR_ACT_NPS_DDR_ALERT_NPS_DDR_BA0PS_DDR_BA1PS_DDR_BG0PS_DDR_BG1PS_DDR_CK_N0PS_DDR_CK_N1PS_DDR_CK0PS_DDR_CK1PS_DDR_CKE0PS_DDR_CKE1PS_DDR_CS_N0PS_DDR_CS_N1PS_DDR_DM0PS_DDR_DM1PS_DDR_DM2PS_DDR_DM3PS_DDR_DM4PS_DDR_DM5

LPDDR3 -bit(Dual Rank)

CA4CA5CA6CA7CA8CA9

LPDDR3 32-bit(Dual Rank)

Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.Can be left unconnected.CK_c

Can be left unconnected.CK_t

Can be left unconnected.CKE0CKE1CS0_nCS1_nDM0DM1DM2DM3

Can be left unconnected.Can be left unconnected.

Zynq UltraScale+ Packaging and PinoutsUG1075 (v1.9) June 24, 2020

Chapter 2:PS Memory Interface Pin Guidelines

Zynq UltraScale+ Packaging and PinoutsUG1075 (v1.9) June 24, 2020

Chapter 2:PS Memory Interface Pin Guidelines

Table 2‐4:

LPDDR3 Supported Pinout Configurations) (Cont’d)

LPDDR3 -bit

DQS2_t_BDQS3_t_B

DQS_t_ECC, can be left unconnected without ECC.ODT_A and ODT_BODT_CA_B

Can be left unconnected.Can be left unconnected.Connect a 240 resistor to GND.(2)

Pin Name

PS_DDR_DQS_P6PS_DDR_DQS_P7PS_DDR_DQS_P8PS_DDR_ODT0PS_DDR_ODT1PS_DDR_PARITYPS_DDR_RAM_RST_NPS_DDR_ZQ

LPDDR3 -bit(Dual Rank)

DQS2_t_BDQS3_t_B

DQS_t_ECC, can be left unconnected without ECC.ODT_A and ODT_BCan be left unconnected.Can be left unconnected.Can be left unconnected.Connect a 240 resistor to GND.(2)

LPDDR3 32-bit(Dual Rank)

Can be left unconnected.Can be left unconnected.DQS_t_ECC, can be left unconnected without ECC.ODT

Can be left unconnected.Can be left unconnected.Can be left unconnected.Connect a 240 resistor to GND.(2)

Zynq UltraScale+ Packaging and PinoutsUG1075 (v1.9) June 24, 2020