FPGA可编程逻辑器件芯片XC5VLX50T-1FF1136I中文规格书

Xilinx provides the diameter of a land pad on the component side. This information is required prior to the start of the board layout so the board pads can be designed to match the component-side land geometry. The typical values of these land pads are described in Figure5-1 and summarized in Table5-1. For Xilinx® BGA packages, Non-Solder Mask Defined (NSMD) pads on the board are suggested to allow a clearance between the land metal (diameter L) and the solder mask opening (diameter M) as shown in Figure5-1. The space between the NSMD pad and the solder mask as well as the actual signal trace widths depend on the capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces are smaller.

VLVHWDLMMask Opening outside of LandeNotes: UG195_C5_01_0105091.3x3 matrix is shown for illustration purposes only. One land pad is shown with via connection.

Figure 5-1:Suggested Board Layout of Soldered Pads for BGA Packages

Virtex-5 FPGA Packaging and Pinout Specification

Power Management Strategy

•Heat Sinking Solutions at the System Level

Depending on the system's physical as well as mechanical constraints, the expectationis that the thermal budget is maintained with custom or OEM heat sink solutions,providing the third prong in the thermal management strategy. At this point, Xilinxhas left the heat sink solution to the system-level designers who can tailor the designand solution to the constraints of their systems, being fully aware that the part hascertain inherent capabilities for delivering the heat to the surface.

Heat sink solutions do exist and can be effective on these low θJB flip-chip platforms.Table6-3 below illustrates a finned heat sink solution matrix in Network environment(1U and 2U) arrangement for 35mm packages and up for power ranging from 15W to40W. The AAVID standard finned heat sink offerings are used to illustrate the coverage given thermal budgets of ΔT=35°C and ΔT=45°C scenarios. Other heat sinkconfigurations can be explored similarly.

Table 6-3:Finned Heat Sink Solution Matrix for Large Flip-chip BGA in NetworkPackage Power

(W)

1U(5)2U(6)1U(5)2U(6)1U(5)2U(6)1U(5)2U(6)

Note4 Note2 Note4 Note4

35 x 35 mm

FF1136/FF1153/FF1156ΔT=35°C

Note 1Note 1

Note2 Note1 Note3 Note2––

Note4 Note2 Note4 Note4

Note 4Note 3

ΔT=45°C

42.5 x 42.5 mm

FF1738/FF1759/FF1760ΔT=35°C

Note 1Note 1

Note2 Note1 Note3 Note2

Note 3Note 2ΔT=45°C

15W

25W

35W

40W

Notes:

1.

2.3.4.5.6.

Solution available at 200 LFM, for example, AAVID finned part number 68520, 72390, 72415.Solution available at 400 LFM, for example, AAVID finned part number 68520, 69920.

Solution available at 600 LFM, for example, AAVID finned part number 72390, 69920, 74590.No standard. AAVID finned solution below 600 LFM—custom finned might be required.For 1U Height—(max heat sink height = 26mm)For 2U Height—(max heat sink height = mm

The Virtex-5 FPGA packages can be grouped into medium- and high-performance

packages based on their power handling capabilities. All Virtex-5 FPGA packages can use thermal enhancements, ranging from simple airflow to schemes that can include passive as well as active heat sinks. This is particularly true for the bigger flip-chip BGA packages where system designers have the option to further enhance the packages with bigger and more elaborate heat sinks to handle excesses of 25W with arrangements that consider system –physical constraints as illustrated in Table6-3.

Virtex-5 FPGA Packaging and Pinout Specification

Chapter 2:Pinout Tables

Virtex-5 FPGA Packaging and Pinout Specification

FF1153 Package—LX50, LX85, LX110, and LX155

Table 2-6:FF1153 Package—LX50, LX85, LX110, and LX155 (Continued)

Bank

Pin Description

Pin Number

W24V24Y26W26V25W25Y27W27V30W30V28V27W31Y31W29V29Y28Y29AB31AA31AC30AB30AA29AA30AD31AE31AD30AC29AF31AG31AE29AD29AJ31

No Connect (NC)

171717171717171717171717171717171717171717171717171717171717171717

IO_L0P_17 IO_L0N_17 IO_L1P_17 IO_L1N_17 IO_L2P_17 IO_L2N_17 IO_L3P_17 IO_L3N_17 IO_L4P_17 IO_L4N_VREF_17

IO_L5P_17 IO_L5N_17 IO_L6P_17 IO_L6N_17 IO_L7P_17 IO_L7N_17 IO_L8P_CC_17 IO_L8N_CC_17(2)IO_L9P_CC_17 IO_L9N_CC_17(2)IO_L10P_CC_17 IO_L10N_CC_17(2)IO_L11P_CC_17 IO_L11N_CC_17(2)IO_L12P_VRN_17 IO_L12N_VRP_17 IO_L13P_17 IO_L13N_17 IO_L14P_17 IO_L14N_VREF_17 IO_L15P_17 IO_L15N_17 IO_L16P_17

Virtex-5 FPGA Packaging and Pinout Specification

Chapter 2:Pinout Tables

Table 2-6:FF1153 Package—LX50, LX85, LX110, and LX155 (Continued)

Bank

Pin Description

Pin Number

AK31AF29AF30AJ30AH30AH29AG30Y11W11W9Y9W10V10V9V8W7V7W5V5Y7Y8Y6W6AA6AA5Y4W4AA4AB5AB6AC5AC4AD4

No Connect (NC)

171717171717171818181818181818181818181818181818181818181818181818

IO_L16N_17 IO_L17P_17 IO_L17N_17 IO_L18P_17 IO_L18N_17 IO_L19P_17 IO_L19N_17 IO_L0P_18 IO_L0N_18 IO_L1P_18 IO_L1N_18 IO_L2P_18 IO_L2N_18 IO_L3P_18 IO_L3N_18 IO_L4P_18 IO_L4N_VREF_18

IO_L5P_18 IO_L5N_18 IO_L6P_18 IO_L6N_18 IO_L7P_18 IO_L7N_18 IO_L8P_CC_18 IO_L8N_CC_18(2)IO_L9P_CC_18 IO_L9N_CC_18(2)IO_L10P_CC_18 IO_L10N_CC_18(2)IO_L11P_CC_18 IO_L11N_CC_18(2)IO_L12P_VRN_18 IO_L12N_VRP_18

Virtex-5 FPGA Packaging and Pinout Specification