W3EG7234S202D3资料

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White Electronic DesignsW3EG7234S-D3

-JD3-AJD3

PRELIMINARY*

256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL

FEATURES

󰀂 Double-data-rate architecture󰀂 Clock speeds: 100MHz and 133MHz󰀂 Bi-directional data strobes (DQS)󰀂 Differential clock inputs (CK & CK#)󰀂 Programmable Read Latency 2,2,5 (clock)󰀂 Programmable Burst Length (2,4,8)

󰀂 Programmable Burst type (sequential & interleave) 󰀂 Edge aligned data output, center aligned data input󰀂 Auto and self refresh󰀂 Serial presence detect󰀂 Power Supply: 2.5V ± 0.20V

󰀂 JEDEC standard 184 pin DIMM package

•

Package height options: JD3: 30.48mm (1.20\") AJD3: 28.70mm (1.13\")

DESCRIPTION

The W3EG7234S is a 32Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR

SDRAM component. The module consists of eighteen 32Mx4 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the

same device to be useful for a variety of high bandwidth, high performance memory system applications.

* This product is under development, is not qualiﬁ ed or characterized and is subject to change without notice.

OPERATING FREQUENCIES

DDR266 @CL=2

Clock SpeedCL-tRCD-tRP

133MHz2-2-2

DDR266 @CL=2.5

133MHz2.5-3-3

DDR200 @CL=2

100MHz2-2-2

December 2004Rev. 2

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White Electronic DesignsPIN CONFIGURATIONS

PIN12345678910111213141516171819202122232425262728293031323334353637383940414243444546

SYMBOLVREFDQ0VSSDQ1DQS0DQ2VCCDQ3NCRESET#VSSDQ8DQ9DQS1VCCQ*CK1*CK1#VSSDQ10DQ11CKE0VCCQDQ16DQ17DQS2VSSA9DQ18A7VCCQDQ19A5DQ24VSSDQ25DQS3A4VCCDQ26DQ27A2VSSA1CB0CB1VCC

PIN47484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192

SYMBOLDQS8A0CB2VSSCB3BA1DQ32VCCQDQ33DQS4DQ34VSSBA0DQ35DQ40VCCQWE#DQ41CAS#VSSDQS5DQ42DQ43VCC*CK2#DQ48DQ49VSS*CK2#*CK2VCCQDQS6DQ50DQ51VSSVCCIDDQ56DQ57VCCDQS7DQ58DQ59VSSNCSDASCL

PIN93949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138

SYMBOLVSSDQ4DQ5VCCQDQS9DQ6DQ7VSSNCNCNCVCCQDQ12DQ13DQS10VCCDQ14DQ15*CKE1VCCQ*BA2DQ20A12VSSDQ21A11DQS11VCCDQ22A8DQ23VSSA6DQ28DQ29VCCQDQS12A3DQ30VSSDQ31CB4CB5VCCQCK0CK0#

PIN139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184

SYMBOLVSSDQS17A10CB6VCCQCB7VSSDQ36DQ37VCCDQS13DQ38DQ39VSSDQ44RAS#DQ45VCCQCS0#*CS1#DQS14VSSDQ46DQ47*CS3#VCCQDQ52DQ53A13*VCCDQS15DQ54DQ55VCCQNCDQ60DQ61VSSDQS16DQ62DQ63VCCQSA0SA1SA2VCCSPD

W3EG7234S-D3

-JD3-AJD3

PRELIMINARY

PIN NAMES

A0 – A12BA0-BA1DQ0-DQ63CB0-CB7DQS0-DQS17CK0CK0#CKE0CS0#RAS#CAS#WE#VCCVCCQVSSVREFVCCSPDSDASCLSA0-SA2VCCIDNC

RESET#

* Not Used

Address input (Multiplexed)Bank Select Address Data Input/OutputCheck bits

Data Strobe Input/OutputClock InputClock Input

Clock Enable InputChip select InputRow Address StrobeColumn Address StrobeWrite EnablePower Supply

Power Supply for DQSGround

Power Supply for ReferenceSerial EEPROM Power SupplySerial data I/OSerial clock

Address in EEPROMVCC Identiﬁ cation FlagNo ConnectReset Enable

December 2004Rev. 2

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White Electronic DesignsFUNCTIONAL BLOCK DIAGRAM

VSSRCS0#DQS0DQ0DQ1DQ2DQ3DQSI/O3I/O2I/O1I/O0CS#DMDQ4DQ5DQ6DQ7I/OI/OI/OI/OW3EG7234S-D3

-JD3-AJD3

PRELIMINARY

DQS9DQS3210CS#DMDQS1DQ8DQ9DQ10DQ11DQSI/O3I/O2I/O1I/O0CS#DMDQS10DQ12DQ13DQ14DQ15I/OI/OI/OI/ODQS3210CS#DMDQS2DQ16DQ17DQ18DQ19I/OI/OI/OI/ODQS3210CS#DMDQS11DQ20DQ21DQ22DQ23I/OI/OI/OI/ODQS3210CS#DMDQS3DQ24DQ25DQ26DQ27DQSI/O3I/O2I/O1I/O0CS#DMDQS12DQ28DQ29DQ30DQ31I/OI/OI/OI/ODQS3210CS#DMDQS4DQSDQ32DQ33DQ34DQ35I/OI/OI/OI/O3210CS#DMDQS13DQ36DQ37DQ38DQ39I/OI/OI/OI/ODQS3210CS#DMCK0SDRAMPLLCK0#REGISTERCS#DMDQS5DQ40DQ41DQ42DQ43DQSI/O3I/O2I/O1I/O0CS#DMDQS14DQ44DQ45DQ46DQ47DQSI/O3I/O2I/O1I/O0DQS6DQSDQ48DQ49DQ50DQ51I/OI/OI/OI/O3210CS#DMDQS15DQ52DQ53DQ54DQ55I/OI/OI/OI/ODQS3210CS#DMSerialPDSCLWPA0SA0DQ60DQ61DQ62DQ63I/OI/OI/OI/ODQS3210CS#DMSDAA1SA1A2SA2DQS7DQ56DQ57DQ58DQ59I/OI/OI/OI/ODQS3210CS#DMDQS16VCCSPDSPDDDR SDRAMDQS8CB0CB1CB2CB3DQSI/O3I/O2I/O1I/O0CS#DMDQS17CB4CB5CB6CB7DQSI/O3I/O2I/O1I/O0CS#DMVCC/VCCQVREFVSSDDR SDRAMDDR SDRAMCS0#BA0-BA1A0-A12RAS#CAS#CKE0WE#PCKPCK#REGISTERRCS0#RBA0 - RBA1RA0 - RA12RRAS#RCAS#RCKE0RWE#RESET#BA0-BA1: DDR SDRAMsA0-A12: DDR SDRAMsRAS#: DDR SDRAMsCAS#: DDR SDRAMsCKE: DDR SDRAMsWE#: DDR SDRAMsNOTE: All resistor values are 22 ohms unless otherwise speciﬁ edDecember 2004Rev. 2

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White Electronic DesignsABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to VSSVoltage on VCC supply relative to VSSStorage TemperaturePower DissipationShort Circuit Current

Note:

W3EG7234S-D3

-JD3-AJD3

PRELIMINARY

SymbolVIN, VOUTVCC, VCCQTSTGPDIOS

Value-0.5 to 3.6-1.0 to 3.6-55 to +150

2750

UnitsVV°C WmA

Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability

DC CHARACTERISTICS

0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V

ParameterSupply VoltageSupply VoltageReference VoltageTermination VoltageInput High VoltageInput Low VoltageOutput High VoltageOutput Low Voltage

SymbolVCCVCCQVREFVTTVIHVILVOHVOL

Min2.32.31.151.15VREF + 0.15-0.3VTT + 0.76—

Max2.72.71.351.35VCCQ + 0.3VREF -0.15—VTT-0.76

UnitVVVVVVVV

CAPACITANCE

TA = 25°C. f = 1MHz, VCC = 2.5V

Parameter

Input Capacitance (A0-A12)Input Capacitance (RAS#,CAS#,WE#)Input Capacitance (CKE0)Input Capacitance (CK0#,CK0)Input Capacitance (CS0#)Input Capacitance (DQS0-DQS17)Input Capacitance (BA0-BA1)

Data input/output capacitance (DQ0-DQ63)(DQS)Data input/output capacitance (CB0-CB7)

SymbolCIN1CIN2CIN3CIN4CIN5CIN6CIN7COUTCOUT

Max6.256.256.255.56.25136.251313

UnitpFpFpFpFpFpFpFpFpF

December 2004Rev. 2

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White Electronic DesignsIDD SPECIFICATIONS AND TEST CONDITIONS

0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V

Includes PLL and Register Power

ParameterOperating Current

SymbolIDD0

Rank 1Conditions

One device bank; Active - Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles.

One device bank; Active-Read-Precharge Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle.

All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (low)

CS# = High; All device banks idle; tCK = tCK (MIN); CKE = High; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM.

One device bank active; Power-Down mode; tCK (MIN); CKE = (low)

CS# = High; CKE = High; One device bank; Active-Precharge;tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle.

Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); lOUT = 0mA.

Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle.tRC = tRC (MIN)CKE ≤ 0.2V

Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands.

W3EG7234S-D3

-JD3-AJD3

PRELIMINARY

DDR266@CL=2

Max

2520

DDR266@CL=2.5

Max

2385

DDR200@CL=2

Max

2385

UnitsmA

Operating CurrentIDD1

270054

252054

mAmA

Precharge Power-Down Standby CurrentIdle Standby Current

IDD2PIDD2F

112010301030mA

Active Power-Down Standby Current Active Standby Current

IDD3P IDD3N

450360360mA

121011201120mA

Operating CurrentIDD4R

274526102610mA

Operating CurrentIDD4W

270037703294860

256536803114770

256536453464770

mAmAmAmA

Auto Refresh CurrentSelf Refresh CurrentOperating Current

IDD5IDD6IDD7A

December 2004Rev. 2

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White Electronic DesignsIDD SPECIFICATIONS AND TEST CONDITIONS

0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V

Includes DDR SDRAM components only

ParameterOperating Current

SymbolIDD0

Rank 1Conditions

One device bank; Active - Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles.

One device bank; Active-Read-Precharge Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle.

All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (low)

CS# = High; All device banks idle; tCK = tCK (MIN); CKE = High; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM.

One device bank active; Power-Down mode; tCK (MIN); CKE = (low)

Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); lOUT = 0mA.

Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands.

W3EG7234S-D3

-JD3-AJD3

PRELIMINARY

DDR266@CL=2

Max

1935

DDR266@CL=2.5

Max

1800

DDR200@CL=2

Max

1800

UnitsmA

Operating CurrentIDD1

211554

193554

mAmA

Precharge Power-Down Standby CurrentIdle Standby Current

IDD2PIDD2F

810720720mA

Active Power-Down Standby Current Active Standby Current

IDD3P IDD3N

450360360mA

900810810mA

Operating CurrentIDD4R

216020252025mA

Operating CurrentIDD4W

21153150544275

19803060364185

mAmAmAmA

Auto Refresh CurrentSelf Refresh CurrentOperating Current

IDD5IDD6IDD7A

December 2004Rev. 2

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White Electronic DesignsDETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A

IDD1 : OPERATING CURRENT: ONE BANK

1. Typical Case: VCC = 2.5V, T = 25°C2. Worst Case: VCC = 2.7V, T = 10°C

3. Only one bank is accessed with tRC (min), Burst

Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lOUT = 0mA 4. Timing patterns

• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRCD = 2*tCK, tRAg = 5*tCK

Read: A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst

• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst

• DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK

Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst

W3EG7234S-D3

-JD3-AJD3

PRELIMINARY

IDD7A: OPERATING CURRENT: FOUR BANKS

1. Typical Case: VCC = 2.5V, T = 25°C2. Worst Case: VCC = 2.7V, T = 10°C

3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns

• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge

Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5, BL = 4, tRRD = 3*tCK, tRCD = 3*tCK Read with autoprecharge

Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL = 2): tCK = 7.5ns, CL2 = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK

Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst

Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3R (0-3) = Read Bank 0-3

December 2004Rev. 2

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White Electronic DesignsW3EG7234S-D3

-JD3-AJD3

PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS

0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V

AC CharacteristicsParameter

Access window of DQs from CK, CK#CK high-level widthCK low-level widthClock cycle time

DQ and DM input hold time relative to DQSDQ and DM input setup time relative to DQSDQ and DM input pulse width (for each input)Access window of DQS from CK, CK#DQS input high pulse widthDQS input low pulse width

DQS-DQ skew, DQS to last DQ valid, per group, per accessWrite command to ﬁ rst DQS latching transitionDQS falling edge to CK rising - setup timeDQS falling edge from CK rising - hold timeHalf clock period

Data-out high-impedance window from CK, CK#Data-out low-impedance window from CK, CK#Address and control input hold time (fast slew rate)Address and control input set-up time (fast slew rate)Address and control input hold time (slow slew rate)Address and control input setup time (slow slew rate)Address and control input pulse width (for each input)LOAD MODE REGISTER command cycle time

DQ-DQS hold, DQS to ﬁ rst DQ to go non-valid, per accessData hold skew factor

ACTIVE to PRECHARGE command

ACTIVE to READ with Auto precharge commandACTIVE to ACTIVE/AUTO REFRESH command periodAUTO REFRESH command period

CL=2.5CL=2

SymboltACtCHtCLtCK (2.5)tCK (2)tDHtDStDIPWtDQSCKtDQSHtDQSLtDQSQtDQSStDSStDSHtHPtHZtLZtIHftISftIHstISstIPWtMRDtQHtQHStRAStRAPtRCtRFC

40156075-0.750.900.90112.215

tHP-tQHS

0.75120,000

40207080

0.750.20.2

tCH, tCL

+0.75

-0.81.11.11.11.12.216 tHP-tQHS

1120,000

Min-0.750.450.457.57.5/100.50.51.75-0.750.350.35

0.51.25

0.750.20.2

tCH, tCL

+0.8

+0.75262/265

Max+0.750.550.551313

Min-0.80.450.458100.60.62-0.80.350.35

0.61.25+0.8202

Max+0.80.550.551313

UnitsnstCKtCKnsnsnsnsnsnstCKtCKnstCKtCKtCKnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

211513,14188,198,20666613,141616222214,1714,1717Notes

December 2004Rev. 2

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White Electronic DesignsW3EG7234S-D3

-JD3-AJD3

PRELIMINARY

DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND

RECOMMENDED AC OPERATING CONDITIONS (continued)

0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V

AC CharacteristicsParameter

ACTIVE to READ or WRITE delayPRECHARGE command periodDQS read preambleDQS read postamble

ACTIVE bank a to ACTIVE bank b commandDQS write preamble

DQS write preamble setup timeDQS write postambleWrite recovery time

Internal WRITE to READ command delayData valid output window

REFRESH to REFRESH command intervalAverage periodic refresh intervalTerminating voltage delay to VCC

Exit SELF REFRESH to non-READ commandExit SELF REFRESH to READ command

SymboltRCDtRPtRPREtRPSTtRRDtWPREtWPREStWPSTtWRtWTRNAtREFCtREFItVTDtXSNRtXSRD

075200Min15150.90.4120.2500.4151

tQH-tDQSQ

140.615.6

080200

0.61.10.6

262/265

Max

Min20200.90.4150.2500.4151

tQH-tDQSQ

140.615.60.61.10.6202

Max

UnitsnsnstCKtCKnstCKnstCKnstCK nsμsμsnsnstCK

13121210,11919Notes

December 2004Rev. 2

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White Electronic DesignsNotes

All voltages referenced to VSS

2. Tests for AC timing, IDD, and electrical AC and DC characteristics

may be conducted at normal reference / supply voltage levels, but the related speciﬁ cations and device operations are guaranteed for the full voltage range speciﬁ ed.3.

Outputs are measured with equivalent load:

W3EG7234S-D3

-JD3-AJD3

PRELIMINARY

11. It is recommended that DQS be valid (HIGH or LOW) on or before

the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS.12. The refresh period is 64ms. This equates to an average refresh

rate of 15.625µs. However, an AUTO REFRESH command must be asserted at least once every 140.6µs; burst refreshing or

posting by the DRAM controller greater than eight refresh cycles is not allowed.13. The valid data window is derived by achieving other speciﬁ cations

- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55.14. Referenced to each output group: x4 = DQS with DQ0-DQ3.15. READs and WRITEs with auto precharge are not allowed to be

issued until tRAS (MIN) can be satisﬁ ed prior to the internal precharge command being issued.16. JEDEC speciﬁ es CK and CK# input slew rate must be > 1V/ns (2V/ns differentially).17. DQ and DM input slew rates must not deviate from DQS by more

than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain.18. tHP min is the lesser of tCL min and tCH min actually applied to the

device CK and CK# inputs, collectively during bank active.19. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX)

condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition.20. For slew rates greater than 1V/ns the (LZ) transition will start about

310ps earlier.21. CKE must be active (High) during the entire time a refresh

command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisﬁ ed.22. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands).

VTTOutput(VOUT) 4.

AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter speciﬁ cations are guaranteed for the speciﬁ ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).The AC and DC input level speciﬁ cations are deﬁ ned in the SSTL_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level).

For slew rates less than 1V/ns and greater than or equal to 0.5V/ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 403 and 335, slew rates must be greater than or equal to 0.5V/ns.Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW.

50ΩReference Point30pF5.

8. tHZ and tLZ transitions occur in the same access time windows as

valid data transitions. These parameters are not referenced to a speciﬁ c voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ).9.

The intent of the “Don’t Care” state after completion of the

postamble is the DQS-driven signal should either be HIGH, LOW, or high-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIHDC (MIN) then it must not transition LOW (below VIHDC) prior to tDQSH (MIN).

10. This is not a device limit. The device will operate with a negative

value, but system performance could be degraded due to bus turnaround.

December 2004Rev. 2

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White Electronic DesignsORDERING INFORMATION FOR JD3

Part NumberW3EG7234S262JD3W3EG7234S265JD3W3EG7234S202JD3

Speed133MHz/266Mb/s133MHz/266Mb/s100MHz/200Mb/s

CAS Latency

22.52

tRCD232

W3EG7234S-D3

-JD3-AJD3

PRELIMINARY

tRP232

Height*30.48 (1.20\")30.48 (1.20\")30.48 (1.20\")

PACKAGE DIMENSIONS FOR JD3

133.48(5.255\" MAX.)131.34(5.171\")128.95(5.077\")3.99(0.157 (2x))3.99(0.157)(MIN)4.06(0.160 MAX)17.78(0.700)10.01(0.394)6.35(0.250)64.77(2.550)1.27(0.050 TYP.)30.48(1.20 MAX)6.35(0.250)1.78(0.070)49.53(1.950)2.31(0.091)(2x)3.00(0.118)(4x)1.27 ± 0.10(0.050 ± 0.004)* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).

December 2004Rev. 2

11White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

元器件交易网www.cecb2b.com

White Electronic DesignsORDERING INFORMATION FOR AJD3

Part NumberW3EG7234S262AJD3W3EG7234S265AJD3W3EG7234S202AJD3

Speed133MHz/266Mb/s133MHz/266Mb/s100MHz/200Mb/s

CAS Latency

22.52

tRCD232

W3EG7234S-D3

-JD3-AJD3

PRELIMINARY

tRP232

Height*28.70 (1.13\")28.70 (1.13\")28.70 (1.13\")

PACKAGE DIMENSIONS FOR AJD3

133.48(5.255\" MAX.)131.34(5.171\")128.95(5.077\")3.99(0.157 (2x))3.99(0.157)(MIN)4.06(0.160 MAX)17.78(0.700)10.01(0.394)6.35(0.250)64.77(2.550)1.27(0.050 TYP.)28.70(1.13 MAX)6.35(0.250)1.78(0.070)49.53(1.950)2.31(0.091)(2x)3.00(0.118)(4x)1.27 ± 0.10(0.050 ± 0.004)* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).

December 2004Rev. 2

12White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

元器件交易网www.cecb2b.com

White Electronic DesignsORDERING INFORMATION FOR D3

Part NumberW3EG7234S262D3W3EG7234S265D3W3EG7234S202D3

Speed133MHz/266Mb/s133MHz/266Mb/s100MHz/200Mb/s

CAS Latency

22.52

tRCD232

W3EG7234S-D3

-JD3-AJD3

PRELIMINARY

tRP232

Height*28.58 (1.125\")28.58 (1.125\")28.58 (1.125\")

PACKAGE DIMENSIONS FOR D3

NOT RECOMMENDED FOR NEW DESIGNS133.48(5.255\" MAX.)131.34(5.171\")128.95(5.077\")3.99(0.157 (2x))3.99(0.157)(MIN)4.06(0.160 MAX)17.78(0.700)10.01(0.394)6.35(0.250)64.77(2.550)1.27(0.050 TYP.)28.58(1.125 MAX)6.35(0.250)1.78(0.070)49.53(1.950)2.31(0.091)(2x)3.00(0.118)(4x)1.27 ± 0.10(0.050 ± 0.004)* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).

December 2004Rev. 2

13White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

元器件交易网www.cecb2b.com

White Electronic DesignsDocument Title

256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL

W3EG7234S-D3

-JD3-AJD3

PRELIMINARY

Revision HistoryRev #

Rev ARev 0

History

Created

0.1 Updated CAP and IDD specs0.2 Removed \"ED\" from Part Marking

0.3 Added JD3 and AJD3 Package Height Options0.4 Moved datasheet from Advanced to Preliminary0.5 Added new Document Title Page

Release Date

5-21-027-04

Status

AdvancedPreliminary

Rev 1Rev 2

1.1 Added AC specs2.1 Updated IDD specs

11-0412-04

PreliminaryPreliminary

December 2004

Rev. 2

14White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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