Low power, ttl level CMOS input buffer with hyster

专利名称：Low power, ttl level CMOS input buffer with

hysteresis

发明人：McAdams, Hugh P.申请号：EP90313086.2申请日：19901203公开号：EP0437039A2公开日：19910717

摘要：A circuit for use as a TTL level CMOS input buffer with hysteresis is disclosed. Afirst transistor (2) of a first conductivity type has its source connected to a first referencevoltage. Second and third transistors (3,4) of opposite conductivity type have their sourcedrain paths connected in series between the drain of the first transistor and a commonpotential. The gates of the first, second, and third transistors are connected to an inputsignal. An inverter (7) has its input connected to the drain of the first transistor and has anoutput. A fourth transistor (5) of the first conductivity type has its gate connected to theoutput, its drain connected to the series connection between the second and thirdtransistors, and its source connected to a second reference voltage. By appropriatelysizing the transistors, the low level trip point and the high level trip point of the circuitmay be adjusted. The circuit draws lower power during standby. Logic gates may also bedesigned that incorporate the circuit.

申请人：TEXAS INSTRUMENTS INCORPORATED

地址：13500 North Central Expressway Dallas Texas 75265 US

国籍：US

代理机构：Abbott, David John

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