LTC6603CUF-TRPBF资料

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LTC6603Dual Adjustable Lowpass FilterFEATURES

Guaranteed Phase and Gain Matching Specsn Programmable BW Up to 2.5MHzn Programmable Gain (0dB/6dB/12dB/24dB)n 9th Order Linear Phase Responsen Differential, Rail-to-Rail Inputs and Outputsn Low Noise: –145dBm/Hz (Input Referred)n Low Distortion: –75dBc at 200kHzn Simple Pin Programming or SPI Interfacen Set the Max Speed/Power with an External Rn Operates from 2.7V to 3.6Vn Input Range from 0V to 5.5Vn 4mm × 4mm QFN PackagenDESCRIPTION

The LTC®6603 is a dual, matched, programmable lowpass ﬁ lter for communications receivers and transmitters. The selectivity of the LTC6603, combined with its linear phase, phase matching and dynamic range, make it suitable for ﬁ ltering in many communications systems. With 1.5° phase matching between channels, the LTC6603 can be used in applications requiring pairs of matched ﬁ lters, such as transceiver I and Q channels. Furthermore, the differential inputs and outputs provide a simple interface for most communications systems.The sampled data ﬁ lter does not require an external clock yet its cutoff frequency can be set with a single external resistor with an accuracy of 3.5% or better. The external resistor programs an internal oscillator whose frequency is divided prior to being applied to the ﬁ lter networks. This allows up to three cutoff frequencies that can be obtained for each external resistor value, allowing the cutoff frequency to be programmed over a range of more than six octaves. Alternatively, the cutoff frequency can be set with an external clock. The ﬁ lter gain can also be programmed to 1, 2, 4 or 16.The LTC6603 features a low power shutdown mode that can be programmed through the serial interface and is available in a 24-pin 4mm × 4mm QFN package.APPLICATIONS

Small/Low Cost Basestations: IDEN, PHS, TD-SCDMA, CDMA2000, WCDMA, UMTSn Low Cost Repeaters, Radio Links, and Modems n 802.11x Receiversn JTRSnL, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.TYPICAL APPLICATION

2.5MHz I and Q Lowpass Filter and Dual ADC5V3V49.9Ω100nH*0.1μF0.1μFI OUTPUTV+INIINQIN0.1μF+INA–INA+INB–INBRBIASVOCM0.1μFCAPGAIN1GAIN0GNDGNDBASEBANDGAIN CONTROLCLKCNTLSDOSDILPFOLPF16603 TA01aLTC2297180pF180pF10pF14-BITADC10pFPhase Matching605040

VS = 3V, BW = 156.25kHzf = 125kHz, TA = 25°C1000 UNITSV+AV+D+OUTA–OUTA+OUTB49.9Ω100nH*LTC6603–OUTBCLKIO49.9Ω100nH*180pFQ OUTPUT180pF10pF14-BITADC10pFVCM2.2μFUNITS (%)302010

–2.5–2–1.5–1–0.500.51MISMATCH (DEG)

30.9kSER49.9Ω100nH*3V1.522.56603 TA01b

3V*COILCRAFT 0603HP6603f1元器件交易网www.cecb2b.com

LTC6603ABSOLUTE MAXIMUM RATINGS

(Note 1)PIN CONFIGURATION

TOP VIEW

GAIN0(D0)+OUTA18–OUTA17SER

16V+D15CLKIO14GND13+OUTB

7+INB8–INB9101112LPFO(SCLK)–OUTBSDOSDIGAIN1+INA–INAV+IN to GND ................................................................6VV+A, V+D to GND .........................................................4VV+A to V+D ..............................................–0.3V to +0.3VFilter Inputs to GND .......................–0.3V to V+IN + 0.3VPins 3, 4 to GND .............................–0.3V to V+A + 0.3VPins 5, 6, 9-11, 15, 17, 21, 22 to GND .................–0.3V to V+D + 0.3VMaximum Input Current .......................................±10mAOutput Short Circuit Duration...........................Indeﬁ niteOperating Temperature Range (Note 2) LTC6603CUF .......................................–40°C TO 85°C LTC6603IUF ........................................–40°C TO 85°CSpeciﬁ ed Temperature Range (Note 3) LTC6603CUF ...........................................0°C TO 70°C LTC6603IUF ........................................–40°C TO 85°CStorage Temperature Range ...................–65°C to 150°C242322212019

V+IN1V+A2VOCM3RBIAS4CLKCNTL5LPF1(CS)6

UF PACKAGE

24-LEAD (4mm × 4mm) PLASTIC QFN

TJMAX = 150°C, θJA = 37°C/W, θJC = 4.3°C/WEXPOSED PAD (PIN 25) IS GND. MUST BE SOLDERED TO THE PCB.ORDER INFORMATION

LEAD FREE FINISHLTC6603CUF#PBFLTC6603IUF#PBFTAPE AND REELLTC6603CUF#TRPBFLTC6603IUF#TRPBFPART MARKING*66036603PACKAGE DESCRIPTIONSPECIFIED TEMPERATURE RANGE24-Lead (4mm × 4mm) Plastic QFN0°C to 70°C24-Lead (4mm × 4mm) Plastic QFN–40°C to 85°CConsult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/ The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.PARAMETERFilter Gain Either ChannelCONDITIONSExternal Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 62.5kHz (0.4 • fC), Relative to DC Gain fIN = 125kHz (0.8 • fC), Relative to DC Gain fIN = 156.25kHz (fC), Relative to DC Gain fIN = 234.375kHz (1.5 • fC), Relative to DC GainExternal Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 62.5kHz (0.4 • fC) fIN = 125kHz (0.8 • fC) fIN = 156.25kHz (fC)MINTYPMAXUNITSELECTRICAL CHARACTERISTICS

lllllllll0.25–0.50.4–0.6CAP0.4–0.30.6–0.4–32±0.03±0.03±0.03±0.030.55–0.10.8–0.2–29.5±0.1±0.1±0.1±0.15dBdBdBdBdBdBdBdBdBMatching of Filter Gain6603f2元器件交易网www.cecb2b.com

LTC6603E LECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating PARAMETERFilter Phase Either ChannelCONDITIONSExternal Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open fIN = 62.5kHz (0.4 • fC) fIN = 125kHz (0.8 • fC) fIN = 156.25kHz (fC)External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open fIN = 62.5kHz (0.4 • fC) fIN = 125kHz (0.8 • fC) fIN = 156.25kHz (fC)External Clock = 80MHz, Filter Cutoff (fC)= 2.5MHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 1MHz (0.4 • fC), Relative to DC Gain fIN = 2MHz (0.8 • fC), Relative to DC Gain fIN = 2.5MHz (fC), Relative to DC Gain fIN = 4MHz (1.5 • fC), Relative to DC GainExternal Clock = 80MHz, Filter Cutoff (fC)= 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 2MHz (0.8 • fC) fIN = 2.5MHz (fC)External Clock = 80MHz, Filter Cutoff (fC)= 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 1MHz (0.4 • fC) fIN = 2MHz (0.8 • fC) fIN = 2.5MHz (fC)External Clock = 80MHz, Filter Cutoff (fC)= 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 1MHz (0.4 • fC) fIN = 2MHz (0.8 • fC) fIN = 2.5MHz (fC)lllllllllllllllllllllllllllllltemperature range, otherwise speciﬁ cations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.MIN158–44–152TYP161–39–146±0.2±0.4±0.50–2–0.7–1.10.5–0.80.40.1–43±0.05±0.2150–45–152155–39–141MAX163–36–142±1.5±3±41.2–0.11.51–32.6±0.2±0.4159–28–126±2.5±4±4±3±3±3.505.611.222.50.5611.823.2±0.1±0.05±0.05±0.1–124–129–135–145–53–59–65–76–751.651.26.612.524±0.2±0.1±0.15±0.2UNITSdegdegdegdegdegdegdBdBdBdBdBdBdBdegdegdegdegdegdeg%%%dBdBdBdBdBdBdBdBdBm/HzdBm/HzdBm/HzdBm/HzdBmdBmdBmdBmdBkΩkΩ6603fMatching of Filter PhaseFilter Gain Either ChannelMatching of Filter GainFilter Phase Either ChannelMatching of Filter PhaseFilter Cutoff Accuracy CLKCNTL = 3V (Note 4)when Self Clocked RBIAS = 200k RBIAS = 54.9k RBIAS = 30.9kDC GainFilter Cutoff (fC) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open Gain Setting = 0dB Gain Setting = 6dB Gain Setting = 12dB Gain Setting = 24dBFilter Cutoff (fC) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open Gain Setting = 0dB Gain Setting = 6dB Gain Setting = 12dB Gain Setting = 24dBVoltage Noise Referred to the Input Gain = 0dB Gain = 6dB Gain = 12dB Gain = 24dBNoise Bandwidth = 5MHz, Referred to the Input Gain = 0dB Gain = 6dB Gain = 12dB Gain = 24dBVIN = 2VP-P, fIN = 200kHz, Gain Setting = 24dBGain = 24dB, RBIAS = 30.9k, Filter Cutoff (fC) = 2.5MHz Differential Common ModeDC Gain MatchingNoise At 200kHzIntegrated NoiseTHDInput Impedance3元器件交易网www.cecb2b.com

LTC6603E LECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating PARAMETERVOS DifferentialCONDITIONSInput Referred Differential Offset Voltage at Either OutputLowest Cutoff Frequency, Gain Setting = 24dBHighest Cutoff Frequency, Gain Setting = 24dBLowest Cutoff Frequency, Gain Setting = 0dBHighest Cutoff Frequency, Gain Setting = 0dBfC = 625kHz Common Mode Input from 0 to 3V, V+IN = 3V Common Mode Input from 0 to 5V, V+IN = 5VV+A = V+D = 3V, Pin 3 OpenV+A = V+D = 3V, Pin 3 OpenCommon Mode Offset Voltage, VOCM = 1.5V, Supplies = 3VVOSCM = VOUT-CM – VOCMSource 1mA, Relative to V+ASink 1mA, Relative to GNDSourcingSinkingInternal Clock (RBIAS = 30.9k); Sum of the Currents into V+D, V+A, and V+IN All Supplies Set to 3V fC = 156.25kHz fC = 625kHz fC = 2.5MHzSum of the Currents into V+D, V+A, and V+IN; All Supplies Set to 3VShutdown Via Serial InterfaceV+D, V+A Relative to GNDV+IN Relative to GNDV+D = V+A = V+IN, All from 2.7V to 3.6VV+D = V+A = 3V, V+IN from 4.5V to 5.5Vllllllllllllltemperature range, otherwise speciﬁ cations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.MINTYPMAX±8±14±40±6060601.32.590901.453.410020015071125301.54.5185500400UNITSmVmVmVmVdBdBVkΩmVmVmVmAmACMRR DifferentialVOCM Pin VoltageVOCM Pin Input Impedance VOSCMOutput SwingShort-Circuit CurrentSupply Currentllllllllll881211621702.72.7406530.954.91.17405085961301752353.65.5mAmAmAμAVVdBdBSupply Current, Shutdown ModeSupply VoltagePSRRRBIAS Resistor RangeCLKCNTL = 3VClock Frequency Error < ±3.5%Clock Frequency Error < ±3%RBIAS Pin Voltage30.9k < RBIAS < 200kClock Frequency Drift RBIAS = 30.9kCLKCNTL Pin OpenOver TemperatureClock Frequency Drift V+A, V+D from 2.7V to 3.6V, RBIAS = 30.9kOver SupplyCLKCNTL Pin OpenOutput Clock Duty CycleRBIAS = 30.9k54.9200kΩkΩVppm/ºCllll0.245V+D – 0.3500.555%/V%VCLKIO Pin High Level CLKCNTL = 0V (Note 5)Input VoltageCLKIO Pin Low Level CLKCNTL = 0V (Note 5)Input VoltageCLKIO Pin Input CurrentCLKCNTL = 0V CLKIO = 0V (Note 6) CLKIO = V+D0.3Vll–1102.952.9μAμAVVCLKIO Pin High Level V+A = V+D = 3V, CLKCNTL = 3VOutput Voltage IOH = –1mA IOH = –4mA6603f4元器件交易网www.cecb2b.com

LTC6603E LECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating PARAMETERCONDITIONSMINTYP0.050.10.30.3llllltemperature range, otherwise speciﬁ cations are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.MAXUNITSVVnsnsV0.3–102V+D – 0.50.5llCLKIO Pin Low Level V+A = V+D = 3V, CLKCNTL = 3V IOL = 1mAOutput Voltage IOL = 4mACLKIO Pin Rise TimeCLKIO Pin Fall TimeSER High Level Input VoltageSER Low Level Input VoltageSER Input CurrentV+A = V+D = CLKCNTL = 3V, CLOAD = 5pFV+A = V+D = CLKCNTL = 3V, CLOAD = 5pFPin 17Pin 17Pin 17 = 0V (Note 6)Pin 17 = V+DV+D – 0.3VμAμAVVμAμACLKCNTL High Level Pin 5Input VoltageCLKCNTL Low Level Input VoltageCLKCNTL Input CurrentPin 5CLKCNTL = 0V (Note 6)CLKCNTL = V+D–25–151525Pin Programmable Control Mode Speciﬁ cations. Speciﬁ cations apply to pins 6, 9, 21 and 22 in pin programmable control mode.SYMBOLV+D = 2.7V to 3.6VVIHVILIINDigital Input High VoltageDigital Input Low VoltageDigital Input CurrentPins 6, 9, 21, 22Pins 6, 9, 21, 22Pins 6, 9, 21, 22 (Note 6)lllPARAMETERCONDITIONSMIN2TYPMAXUNITSV0.8–11VμASerial Port DC and Timing Speciﬁ cations. Speciﬁ cations apply to pins 6, 9-11, and 21 in serial programming mode.SYMBOLV+D = 2.7V to 3.6VVIHVILIINVOHVOLt1 (Note 5)t2 (Note 5)t3t4t5t6 (Note 5)t7 (Note 5)t8t9 (Note 5)Digital Input High VoltageDigital Input Low VoltageDigital Input CurrentDigital Output High VoltageDigital Output Low VoltageSDI Valid to SCLK SetupSDI Valid to SCLK HoldSCLK LowSCLK HighCS Pulse WidthLSB SCLK to CSCS Low to SCLKSDO Output DelaySCLK Low to CS LowCL = 15pFPins 6, 9, 10Pins 6, 9, 10Pins 6, 9, 10 (Note 6)Pins 11, 21 Sourcing 500μAPins 11, 21 Sinking 500μAllllllllllllllPARAMETERCONDITIONSMIN2TYPMAXUNITSV0.8–1VSUPPLY – 0.30.360010010060603012501VμAVVnsnsnsnsnsnsnsnsns6603f5元器件交易网www.cecb2b.com

LTC6603ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: LTC6603C and LTC6603I are guaranteed functional over the operating temperature range of –40°C to 85°C.Note 3: LTC6603C is guaranteed to meet speciﬁ ed performance from 0°C to 70°C. The LTC6603C is designed, characterized and expected to meet speciﬁ ed performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LTC6603I is guaranteed to meet the speciﬁ ed performance limits from –40°C to 85°C. Note 4: This test measures the internal oscillator accuracy (deviation from the fCLK equation). Variations in the internal oscillator cause variations in the ﬁ lter cutoff frequency. See the “Applications Information” section.Note 5: Guaranteed by design, not subject to test.Note 6: To conform to the logic IC standard, current out of a pin is arbitrarily given a negative value.TYPICAL PERFORMANCE CHARACTERISTICS

DC Gain Matching70

VS = 3V, BW = 2.5MHzGAIN SETTING = 0dB, TA = 25°C601000 UNITS50

UNITS (%)UNITS (%)40302010

–0.2–0.15–0.1–0.0500.050.10.150.2

MISMATCH (dB)

6603 G01

DC Gain Matching70

VS = 3V, BW = 156.25kHzGAIN SETTING = 0dB, TA = 25°C601000 UNITS5040302010

–0.06–0.04–0.0200.020.040.060.080.1

MISMATCH (dB)

6603 G02

Phase Matching302520UNITS (%)15105

–2.5–2–1.5–1–0.500.511.522.533.54

MISMATCH (DEG)

6603 G03

VS = 3V, BW = 2.5MHzf = 2MHz, TA = 25°C1000 UNITSPhase Matching605040UNITS (%)35302010

–2.5–2–1.5–1–0.500.51

MISMATCH (DEG)

GAIN (dB)VS = 3V, BW = 156.25kHzf = 125kHz, TA = 25°C1000 UNITS3020100–10–20–30–40–50

Gain and Group Delay vs Frequency800

GAIN = 24dB760720

GAIN = 0dBGAIN = 12dBGAIN = 6dBGROUP DELAY68064060056052048044040010M

6603 G05

GROUP DELAY (ns)1.522.5

RBIAS = 30.9k, VS = 3V–60LPF1 = 1, BW = 2.5MHzTA = 25°C–7010k100k1M

FREQUENCY (Hz)

6603 G04

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LTC6603TYPICAL PERFORMANCE CHARACTERISTICS

Gain and Group Delay vs Frequency3020100GAIN (dB)–10–20

–30GROUP DELAY–40

RBIAS = 30.9k, VS = 3V–50LPF1 = 0, LPF0 = 1,–60BW = 625kHzTA = 25°C–7010k100k1MFREQUENCY (Hz)

GAIN = 0dBGAIN = 24dBGAIN = 12dBGAIN = 6dB3.53.33.12.92.72.52.32.11.91.71.510M6603 G06

Gain and Group Delay vs Frequency3020100GAIN (dB)–10–20–30–40

RBIAS = 30.9k, VS = 3V–50LPF1 = LPF0 = 0,–60BW = 156.25kHzTA = 25°C–70

1k10k100kFREQUENCY (Hz)

GROUP DELAY (ns)GAIN = 12dBGAIN = 6dBGAIN = 0dBGROUP DELAYGAIN = 24dB12.011.511.0

DISTORTION (dBc)10.510.09.59.08.58.07.57.01M6603 G07

Distortion vs Input Frequency–50

RBIAS = 30.9k, VS = 3VLPF1 = 1, BW = 2.5MHzVOUT = 2VP-P, TA = 25°CHD3, GAIN = 24dBHD3, GAIN = 0dB–70

HD2, GAIN = 0dB–80

HD2, GAIN = 24dB–60

GROUP DELAY (μs)–90100

50090013001700INPUT FREQUENCY (kHz)

6603 G08

Distortion vs Input Frequency–60–65DISTORTION (dBc)–70–75–80–85–90100

RBIAS = 54.9k, VS = 3VLPF1 = 1, BW = 1.41MHzTA = 25°CDISTORTION (dBc)HD3, GAIN = 0dB–60

Distortion vs Input FrequencyRBIAS = 30.9k, VS = 3VLPF1 = 0, LPF0 = 1, BW = 625kHz–65VOUT = 2VP-P, TA = 25°CHD3, GAIN = 0dBDISTORTION (dBc)–70–75–80–85–90

HD2, GAIN = 24dBHD2, GAIN = 0dB20

120

220420320

INPUT FREQUENCY (kHz)

520

6603 G10

Distortion vs Input Frequency–70

HD3, GAIN = 0dB–75–80

HD2, GAIN = 24dB–85

HD2, GAIN = 0dB–90

HD3, GAIN = 24dBHD3, GAIN = 24dBHD2, GAIN = 0dBHD2, GAIN = 24dBHD3, GAIN = 24dB300

700500900

INPUT FREQUENCY (kHz)

1100

6603 G09

–95RBIAS = 30.9k, VS = 3VLPF1 = LPF0 = 0, BW = 156.25kHzVOUT = 2VP-P, TA = 25°C–100

5090110130103070

INPUT FREQUENCY (kHz)

150

6603 G11

Distortion vs Output VoltageFILTER CUTOFF FREQUENCY DEVIATION (%)–60

RBIAS = 30.9k, VS = 3V, LPF1 = 0, LPF0 = 1, BW = 2.5MHz, GAIN = 24dB, TA = 25°CHD3, f = 1MHzHD2, f = 1MHz–80

0.20.10.0–0.1–0.2–0.3–0.4–0.5–0.6–0.7

Filter Cutoff Accuracy vs Supply VoltageFILTER CUTOFF FREQUENCY DEVIATION (%)LPF1 = LPF0 = 0, BW = 156.25kHz1.0

Filter Cutoff Accuracyvs TemperatureVS = 3V0.8RBIAS = 30.9k 0.60.40.20.0–0.2–0.4–0.6–0.8

–50

–30

BW = 2.5MHzBW = 156.25kHzBW = 625kHz–70DISTORTION (dBc)LPF1 = 0, LPF0 = 1,BW = 625kHzLPF1 = 1, BW = 2.5MHz–90

HD3, f = 200kHzHD2, f = 200kHz–100

1.01.21.41.61.82.02.22.42.62.83.0

OUTPUT VOLTAGE (VP-P)

6603 G11

–0.8RBIAS = 30.9k TA = 25°C–0.9

2.72.82.93.03.13.23.33.43.53.6

SUPPLY VOLTAGE (V)

6603 G13

–10103050TEMPERATURE (°C)

7090

6603 G14

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LTC6603TYPICAL PERFORMANCE CHARACTERISTICS

Common Mode Rejection Ratio1009080

CMRR (dB)CMRR (dB)70605040

VS = 3V, RBIAS = 30.9k30LPF1 = 1, BW = 2.5MHzTA = 25°C2010k100k1M

FREQUENCY (Hz)

GAIN = 12dBGAIN = 24dBGAIN = 0dBGAIN = 6dB11010090

80GAIN = 6dB7060504030

10M

6603 G15

Common Mode Rejection RatioVS = 3V, RBIAS = 30.9kLPF1 = 0, LPF0 = 1,BW = 625kHz, TA = 25°CGAIN = 24dBGAIN = 0dBGAIN = 12dBCMRR (dB)1201101009080706050

Common Mode Rejection RatioGAIN = 24dBGAIN = 12dBGAIN = 0dBGAIN = 6dB2010k100k1MFREQUENCY (Hz)10M6603 G16

VS = 3V, RBIAS = 30.9k40LPF1 = LPF0 = 0, BW = 156.25kHz,TA = 25°C301k10k100k

FREQUENCY (Hz)

6603 G17

Common Mode Rejection100COMMON MODE REJECTION (dB)90

80GAIN = 6dB70

GAIN = 12dB6050

40VS = 3V, RBIAS = 30.9kLPF1 = 1, BW = 2.5MHz,TA = 25°C3010k100k1M

FREQUENCY (Hz)

GAIN = 24dBCMR = ΔVIN-CM/ΔVOUT-DIFFGAIN = 0dBCOMMON MODE REJECTION (dB)11010090807060

Common Mode RejectionCOMMON MODE REJECTION (dB)VS = 3V, RBIAS = 30.9kLPF1 = 0, LPF1 = 1, BW = 625kHz,TA = 25°CGAIN = 0dBGAIN = 6dB100

Common Mode RejectionGAIN = 12dB90

GAIN = 24dBGAIN = 0dB70

GAIN = 6dBCMR = ΔVIN-CM/ΔVOUT-DIFFVS = 3V, RBIAS = 30.9kLPF1 = LPF0 = 0, BW = 156.25kHz,TA = 25°C1k

10k100kFREQUENCY (Hz)

6603 G20

GAIN = 12dBGAIN = 24dB60

10M

6603 G18

CMR = ΔVIN-CM/ΔVOUT-DIFF5010k100k1M

FREQUENCY (Hz)

10M

6603 G19

OIP3 vs Average Signal Frequency41

GAIN = 6dB40

GAIN = 12dB39OIP3 (dBm)OIP3 (dBm)383736

GAIN = 0dB42

GAIN = 24dB4446

OIP3 vs Average Signal Frequency43

GAIN = 12dBGAIN = 0dBGAIN = 6dBOIP3 (dBm)GAIN = 24dB414039383742

OIP3 vs Average Signal FrequencyGAIN = 0dBGAIN = 12dBGAIN = 6dBGAIN = 24dB40

38VS = 3V, RBIAS = 30.9k, TA = 25°CLPF1 = 0, LPF0 = 1, BW = 625kHzVOUT = 6dBm PER TONE FOR 2-TONE TESTΔf = 10kHz360100200300400500600AVERAGE FREQUENCY OF TWO TONES (kHz)

6603 G22

VS = 3V, RBIAS = 30.9k, TA = 25°CLPF1 = 0, LPF0 = 1, BW = 625kHz35

VOUT = 6dBm PER TONE FOR 2-TONE TESTΔf = 10kHz341005009001300170021002500AVERAGE FREQUENCY OF TWO TONES (kHz)

6603 G21

VS = 3V, RBIAS = 30.9k, TA = 25°CLPF1 = 0, LPF0 = 1, BW = 156.25kHz36

VOUT = 6dBm PER TONE FOR 2-TONE TESTΔf = 10kHz3520406080100120140160AVERAGE FREQUENCY OF TWO TONES (kHz)

6603 G23

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LTC6603TYPICAL PERFORMANCE CHARACTERISTICS

OIP3 vs Temperature424140OIP3 (dBm)39BW = 625kHz,FREQUENCY = 200kHz38BW = 156.25kHz,FREQUENCY = 60kHz3736

BW = 2.5MHz, FREQUENCY = 1MHz–30

–10103050TEMPERATURE (°C)

6603 G23

Output Impedance vs Frequency10

VS = 3V, RBIAS = 30.9k, TA = 25°CLPF1 = 0, LPF0 = 1,BW = 625kHzLPF1 = LPF0 = 0,BW = 156.25kHz0.1

200180SUPPLY CURRENT (mA)160140

Supply Current vs Supply VoltageTA = 25°CRBIAS = 30.9k BW = 2.5MHzOUTPUT IMPEDANCE (Ω)VS = 3V, RBIAS = 30.9kPASSBAND GAIN = 24dBVOUT = 6dBm PER TONE FOR 2-TONE TESTΔf = 10kHz1

BW = 625kHz12010080

BW = 156.25kHz0.01LPF1 = 1, BW = 2.5MHz35–50

0.001

1k10k

100k1MFREQUENCY (Hz)

10M

6603 G25

2.72.82.93.03.13.23.33.43.53.6

SUPPLY VOLTAGE (V)

6603 G26

Supply Current vs Temperature180160SUPPLY CURRENT (mA)140

VOLTAGE (V)1201008060–50

BW = 156.25kHzTA = 25°CRBIAS = 30.9k BW = 2.5MHz543210–1

Clock Output Operating at 80MHzRBIAS = 30.9k, VS = 3VTA = 25°C RBIAS PIN VOLTAGE (V)1.25

RBIAS Pin Voltage vs IRBIASTA = 25°CVS = 3V 1.20

BW = 625kHz1.15

–30

–10103050TEMPERATURE (°C)

–2

–14–12–10

–8–6–4TIME (ns)

–202

1.10

6603 G27

1015IRBIAS (μA)

2025

6603 G29

6603 G28

Input Referred Noise Density1000VOLTAGE NOISE DENSITY (nV/√Hz)GAIN = 0dBGAIN = 6dBGAIN = 12dB10

GAIN = 24dBVOLTAGE NOISE DENSITY (nV/√Hz)1000

Input Referred Noise Density1000VOLTAGE NOISE DENSITY (nV/√Hz)Input Referred Noise DensityGAIN = 0dBGAIN = 6dB100

GAIN = 12dBGAIN = 24dB100

GAIN = 0dB100

GAIN = 6dBGAIN = 12dBGAIN = 24dB10

VS = 3V, RBIAS = 30.9kLPF1 = 0, LPF0 = 1,BW = 625kHzTA = 25°C100k1MFREQUENCY (Hz)

10M

6603 G31

VS = 3V, RBIAS = 30.9kLPF1 = 0, LPF0 = 0,BW = 156.25kHzTA = 25°C1k

10k100kFREQUENCY (Hz)

6603 G32

VS = 3V, RBIAS = 30.9kLPF1 = 1, BW = 2.5MHzTA = 25°C100k1MFREQUENCY (Hz)

10M

6603 G30

0.110k110k

6603f9元器件交易网www.cecb2b.com

LTC6603TYPICAL PERFORMANCE CHARACTERISTICS

Integral Input Referred Noise1000

VS = 3V, RBIAS = 30.9kLPF1 = 1,BW = 2.5MHzTA = 25°CVOLTAGE NOISE (μV)GAIN = 6dBGAIN = 0dB1000

Integral Input Referred NoiseVS = 3V, RBIAS = 30.9kLPF1 = 0, LPF0 = 1, BW = 625kHzTA = 25°CGAIN = 0dBVOLTAGE NOISE (μV)GAIN = 6dBGAIN = 12dBGAIN = 24dB10

1000

Integral Input Referred NoiseVS = 3V, RBIAS = 30.9kLPF1 = LPF0 = 0, BW = 156.25kHzTA = 25°CGAIN = 0dBGAIN = 6dBGAIN = 12dBGAIN = 24dB10

VOLTAGE NOISE (μV)100100100

GAIN = 12dBGAIN = 24dB110k

100k1MINTEGRATION BW (Hz)

10M

6603 G33

110k

100k1MINTEGRATION BW (Hz)

10M

6603 G34

110k

100k

INTEGRATION BW (Hz)

6603 G35

PIN FUNCTIONS

V+IN (Pin 1): Input Voltage Supply (2.7V ≤ V ≤ 5.5V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF ca-pacitor unless it is tied to V+A (Pin 2). The bypass should be as close as possible to the IC, but is not as critical as the bypassing of V+A and V+D (Pin16).V+A (Pin 2): Analog Voltage Supply (2.7V ≤ V ≤ 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor. The bypass should be as close as possible to the IC.VOCM (Pin 3): Output common mode voltage reference. If ﬂ oated, an internal resistive divider sets the voltage on this pin to half the supply voltage (typically 1.5V), maximiz-ing the dynamic range of the ﬁ lter. If this pin is ﬂ oated, it must be bypassed with a quality 1μF capacitor to ground. This pin has a typical input impedance of 3.4k and may be overdriven. Driving this pin to a voltage other than the default value will reduce the signal range the ﬁ lter can handle before clipping.RBIAS (Pin 4): Oscillator Frequency-Setting Resistor Input. The value of the resistor connected between this pin and ground determines the frequency of the master oscillator, and sets the bias currents for the ﬁ lter networks. The voltage on this pin is held by the LTC6603 to approximately 1.17V. For best performance, use a precision metal ﬁ lm resis-tor with a value between 30.9k and 200k and limit the capacitance on this pin to less than 10pF. This resistor is necessary even if an external clock is used.CLKCNTL (Pin 5): Clock Control Input. This three-state input selects the function of CLKIO (Pin 15). Tying the CLKCNTL pin to ground allows the CLKIO pin to be driven by an external clock (CLKIO is the master clock input). If the CLKCNTL pin is ﬂ oated, the internal oscillator is enabled, but the master clock is not present at the CLKIO pin (CLKIO is a no-connect). If the CLKCNTL pin is tied to V+D (Pin 16), the internal oscillator is enabled and the master clock is present at the CLKIO pin (CLKIO is the master clock output). To detect a ﬂ oating CLKCNTL pin, the LTC6603 attempts to pull the pin toward mid-supply. This is realized with two internal 15μA current sources, one tied to V+D and CLKCNTL and the other one tied to ground and CLKCNTL. Therefore, driving the CLKCNTL pin high requires sourcing approximately 15μA. Likewise, driving the CLKCNTL pin low requires sinking 15μA. When the CLKCNTL pin is ﬂ oated, it should be bypassed by a 1nF capacitor to ground or be surrounded by a ground shield to prevent excessive coupling from other PCB traces.6603f10元器件交易网www.cecb2b.com

LTC6603PIN FUNCTIONS

LPF1(CS) (Pin 6): TTL Level Input. When in pin program-mable control mode, this pin is the MSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the chip select input (active low).+INB, –INB (Pins 7, 8): Channel B differential inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided.LPF0(SCLK) (Pin 9): TTL Level Input. When in pin program-mable control mode, this pin is the LSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the clock of the serial interface.SDI (Pin 10): TTL Level Input. When in pin programmable control mode, this pin is left ﬂ oating; in serial control mode, this pin is the serial data input.SDO (Pin 11): TTL Level Input. When in pin programmable control mode, this pin is left ﬂ oating; in serial control mode, this pin is the serial data output.–OUTB, +OUTB (Pins 12, 13): Channel B differential ﬁ lter outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100Ω series resistor is recommended for each output. The common mode voltage of the ﬁ lter outputs is the same as the voltage at VOCM (Pin 3).GND (Pin 14): Ground. Should be tied to a ground plane for best performance.CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground, CLKIO is the master clock input. When CLKCNTL is ﬂ oated, CLKIO is pulled to ground by a weak pulldown. When CLKCNTL is tied to V+D (Pin 16), CLKIO is the master clock output. When conﬁ gured as a clock output, this pin can drive 1k and/or 5pF loads (heavier loads will cause inaccuracies).V+D (Pin 16): Digital Voltage Supply (2.7V ≤ V ≤ 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor. The bypass should be as close as possible to the IC.SER (Pin 17): Interface Selection Input. When tied to V+D (Pin 16) or ﬂ oated, the interface is in pin programmable control mode, i.e. the ﬁ lter gain and cutoff frequencies are programmed by the GAIN1, GAIN0, LPF1 and LPF0 pins. When SER is tied to ground, the ﬁ lter gain, the ﬁ lter cutoff frequency and shutdown mode are programmed by the serial interface.–OUTA, +OUTA (Pins 18, 19): Channel A differential ﬁ lter outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100Ω series resistor is recommended for each output. The common mode voltage of the ﬁ lter outputs is the same as the voltage at VOCM (Pin 3).CAP (Pin 20): Connect a 0.1μF bypass capacitor to this pin. Pin 20 is a buffered version of Pin 3.GAIN0(D0) (Pin 21): TTL Level Input. When in pin pro-grammable control mode, this pin is the LSB of the gain control code; in serial control mode, this pin is the LSB of the serial control register, an output.GAIN1 (Pin 22): TTL Level Input. When in pin programmable control mode, this pin is the MSB of the gain control code; in serial control mode, this pin is a no-connect.–INA, +INA (Pins 23, 24): Channel A differential inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided.Exposed Pad (Pin 25): Ground. The Exposed Pad must be soldered to PCB.6603f11元器件交易网www.cecb2b.com

LTC6603BLOCK DIAGRAM

+INA24–INA23GAIN122GAIN0(D0)

21CAP20+OUTA19V+IN1CHANNEL A18–OUTA

GAINV+A2CONTROLV+ABIASLPF17SER

CLKVOCM3TO PIN 2016V+D

CONTROLLOGICCLOCKGENERATOR15CLKIO

BIASCONTROLCLK14GND

GNDRBIAS4BIAS/OSCCLKCNTL5GAINLPFLPF1(CS)6CHANNEL B13+OUTB

7+INB

8–INB

9LPF0(SCLK)

10SDI

11SDO

12–OUTB

6603 BD

TIMING DIAGRAM

t1t2SCLK

Timing Diagram of the Serial Interfacet4t3t6t7t9SDI

D3D2D1D0D7 • • • • D4D3t5CS

t8SDO

D4PREVIOUS BYTE

D3D2D1D0D7 • • • • D4CURRENT BYTE

D36603 TD

6603f12元器件交易网www.cecb2b.com

LTC6603APPLICATIONS INFORMATION

Theory of Operation (Refer to Block Diagram)The LTC6603 features two matched ﬁ lter channels, each containing gain control and lowpass ﬁ lter networks that are controlled by a single control block and clocked by a single clock generator. The gain and cutoff frequency can be separately programmed. The two channels are not independent, i.e. if the gain is set to 24dB then both channels have a gain of 24dB. The ﬁ lter can be clocked with an external clock source, or using the internal oscil-lator. A resistor connected to the RBIAS pin sets the bias currents for the ﬁ lter networks and the internal oscillator frequency (unless driven by an external clock). Altering the clock frequency changes the ﬁ lter bandwidth. This allows the ﬁ lters to be “tuned” to many different bandwidths.Pin Programmable InterfaceAs shown in Figure 1, connecting SER to V+D allows the ﬁ lter to be directly controlled through the pin program-mable control lines GAIN1, GAIN0, LPF1 and LPF0. The GAIN0(D0) pin is bidirectional (input in pin programmable control mode, output in serial mode). In pin programmable control mode, the voltage at GAIN0(D0) cannot exceed V+D; otherwise, large currents can be injected to V+D through the parasitic diodes (see Figure 2). Connecting a 10k resistor at the GAIN0(D0) pin (see Figure 1) is recommended for current limiting, to less than 10mA. SER has an internal 3.3VLTC6603V+INV+AV+Dpull-up to V+D. None of the logic inputs have an internal pull-up or pull-down.Serial InterfaceConnecting SER to ground allows the ﬁ lter to be controlled through the SPI serial interface. When CS is low, the serial data on SDI is shifted into an 8-bit shift-register on the rising edge of the clock (SCLK), with the MSB transferred ﬁ rst (see Figure 3). Serial data on SDO is shifted out on the clock’s falling edge. A high CS will load the 8 bits of the shift-register into an 8-bit D-latch, which is the serial control register. The clock is disabled internally when CS is pulled high. Note: SCLK must be low before CS is pulled low to avoid an extra internal clock pulse. SDO is always active in serial mode (never tri-stated) and cannot be “wire-or’ed” to other SPI outputs. In addition, SDO is not forced to zero when CS is pulled high.An LTC6603 may be daisy chained with other LTC6603s or other devices having serial interfaces. Daisy chain-ing is accomplished by connecting the SDO of the lead chip to the SDI of the next chip, while SCLK and CS remain common to all chips in the daisy chain. The se-rial data is clocked to all the chips then the CS signal is pulled high to update all of them simultaneously. Figure 4 shows an example of two LTC6603s in a daisy chained SPI conﬁ guration.3.3VLTC6603V+INV+AV+D0.1μF0.1μF+–VIN+INA–INASERLPF1(CS)LPF0(SCLK)+OUTA–OUTAVOUT

+–

+–LPF1LPF0μPVIN+INA–INASERLPF1(CS)LPF0(SCLK)+OUTA–OUTAVOUT

+–

GAIN1GAIN0(D0)GNDGAIN1GAIN010kGAIN1GAIN0(D0)GNDLOWPASS CUTOFF = 2.5MHz (fCLK = 80MHz)

GAIN = 4

GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR.10k RESISTORS ON GAIN0(OUT) PROTECTS THE DEVICE WHEN VGAIN0 > V+D

6603 F01

Figure 1. Filter in Pin Programmable Control Mode6603f13元器件交易网www.cecb2b.com

LTC6603APPLICATIONS INFORMATION

SHUTDOWNV+DOUTNO4-BIT GAIN, BWFUNCTIONCONTROL CODECS8-BIT LATCHGAIN0(D0)

SDIQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q78-BITSHIFT-REGISTER(INTERNALNODE)6603 F02SCLKSDO6603 F03Figure 2. Bidirectional Design of GAIN0(OUT) PinFigure 3. Diagram of Serial Interface (MSB First Out)3.3VLTC6603#13.3VLTC6603#20.1μFV+INV+AV+D0.1μFV+INV+AV+D+VIN1+INA–INASER+OUTA–OUTA+–VOUT1+VIN2+INA–INASERLPF1(CS)+OUTA–OUTA+–VOUT2

––CSXμPSCLKSDILPF1(CS)LPF0(SCLK)SDIGNDGAIN0(D0)SDOOUT1LPF0(SCLK)SDIGNDGAIN0(D0)SDOOUT2SDOSCLK

SDID15D11D10D9D8D7D3D2D1D0GAIN, BW CONTROL WORD FOR #2SHUTDOWN FOR #2CS

GAIN, BW CONTROL WORD FOR #1SHUTDOWN FOR #16603 F04

Figure 4. Two Devices in a Daisy ChainSerial Control Register Deﬁ nitionD7GAIN0D6GAIN1D5LPF0D4LPF1D3D2D1SHDND0OUT6603fNO FUNCTIONNO FUNCTION14元器件交易网www.cecb2b.com

LTC6603APPLICATIONS INFORMATION

GAIN1 and GAIN0 are the gain control bits (register bits D6 and D7 when in serial mode). Their function is shown in Table 1. In serial mode, register bit D1 can be set to “1” to put the device into a low power shutdown mode. Register bit D0 is a general purpose output (Pin 21) when in serial mode.Table 1. Gain ControlGAIN 10011GAIN 00101PASSBAND GAIN (dB)061224Self-Clocking OperationThe LTC6603 features a unique internal oscillator which sets the ﬁ lter cutoff frequency using a single external resistor connected to the RBIAS pin. The clock frequency is deter-mined by the following simple formula (see Figure 5): fCLK = 247.2MHz • 10k/RBIASNote: RBIAS ≤ 200kThe design is optimized for V+A, V+D = 3V, fCLK = 45MHz, where the ﬁ lter cutoff frequency error is typically <3% when a 0.1% external 54.9k resistor is used (any resis-tor (RBIAS) tolerance, will shift the clock frequency). With different resistor values and cutoff frequency control set-tings (LPF1 and LPF0), the lowpass cutoff frequency can 200175150RBIAS (kΩ)125100755025

be accurately varied from 24.14kHz to 2.5MHz. Table 2 summarizes the cutoff frequencies that can be obtained with an external resistor (RBIAS) value of 30.9k. Note that the cutoff frequencies scale with the clock frequency. For example, if LPF1 and LPF0 are both equal to zero, and RBIAS is increased from 30.9k to 200k, fCLK will decrease from 80MHz to 12.36MHz and the cutoff frequency will be reduced from 156.25kHz to 24.14kHz. The cutoff frequencies that can be obtained with external resistor values of 54.9k and 200k are shown in Table 3 and Table 4, respectively. When the LTC6603 is programmed for the cutoff frequencies lower than the maximum, the power is automatically reduced. The power savings at the middle bandwidth setting (LPF1 = ‘0’, LPF0 = ‘1’), is about 23%, while the power savings at the lowest bandwidth setting (LPF1 = ‘0’, LPF0 = ‘0’) is about 60%.Table 2. Cutoff Frequency Control, RBIAS = 30.9k, fCLK = 80MHzLPF10011LPF00101LOWPASS BW(kHz)156.2562525002500Table 3. Cutoff Frequency Control, RBIAS = 54.9k, fCLK = 45MHzLPF10011LPF00101LOWPASS BW(kHz)87.94351.7814071407Table 4. Cutoff Frequency Control, RBIAS = 200k, fCLK = 12.36MHzLPF10011LPF00101LOWPASS BW(kHz)24.1496.56386.25386.2510

203040506070DESIRED CLOCK FREQUENCY (MHz)

6603 F05

Figure 5. RBIAS vs Desired Clock Frequency6603f15元器件交易网www.cecb2b.com

LTC6603APPLICATIONS INFORMATION

The following graphs show a few of the possible lowpass ﬁ lters.Gain and Group Delay vs Frequency (2.5MHz Lowpass Response)0–20GAIN (dB)–40–60

GROUP DELAY–80–100–120

100k

0.40.20

6603 G17

Alternative Methods of Setting the Clock Frequency of the LTC6603The oscillator may be programmed by any method that sinks a current out of the RBIAS pin. The circuit in Figure 6 sets the clock frequency by using a programmable current source and in the expression for fCLK, the resistor RBIAS is replaced by the ratio of 1.17V/ICONTROL. Because the voltage of the RBIAS pin is approximately 1.17V ±5%, the Figure 6 circuit is less accurate than if a resistor controls the clock frequency.In this circuit, the LTC2621 (a 12-bit DAC) is daisy chained with the LTC6603. Because the sinking current from the RBIAS pin is 2N•R1

the equivalent RBIAS is2N•R1 k,where k is the binary DAC input code and N is the resolu-tion. Figure 7 shows some of the frequency responses that can be obtained using this circuit.Figure 8 shows the LTC6603’s oscillator conﬁ gured as a VCO. A voltage source is connected in series with the RBIAS resistor. The clock frequency, fCLK, will vary with VCONTROL. Again, this circuit decouples the relationship between the current out of the RBIAS pin and the voltage of the RBIAS pin; the frequency accuracy will be degraded. The clock frequency, however, will increase monotonically with decreasing VCONTROL.Operation Using an External ClockThe LTC6603 may be clocked by an external oscillator for tighter bandwidth control by pulling CLKCNTL (Pin 5) to ground and driving a clock into CLKIO (Pin 15). If an external clock is used, the RBIAS resistor is still necessary. The value of RBIAS must be no larger than the value that would be required for using the internal oscillator. For example, a 100k resistor would program the internal oscil-lator for 24.705MHz, so an external oscillator frequency of 24.705MHz would require an RBIAS resistance of no more 6603fGAIN1.21.0

GROUP DELAY (μs)0.80.6

FREQUENCY (Hz)

10M

VRBIAS•k

Gain and Group Delay vs Frequency (650kHz Lowpass Response)0

GAIN3

GROUP DELAY (μs)–20GAIN (dB)–40GROUP DELAY2

–601

–80100k

FREQUENCY (Hz)

6603 G18

The oscillator is sensitive to transients on the positive supply. The IC should be soldered to the PC board and the PCB layout should include a 0.1μF ceramic capacitor between V+A (Pin 2) and ground, as close as possible to the IC to minimize inductance. The PCB layout should also include an additional 0.1μF ceramic capacitor between V+D (Pin 16) and ground. Avoid parasitic capacitance on RBIAS (Pin 4) and avoid routing noisy signals near RBIAS. Use a ground plane connected to Pin 14 and the Exposed Pad (Pin 25).16元器件交易网www.cecb2b.com

LTC6603APPLICATIONS INFORMATION

–INB5VI RANGE = 6μA TO 38.4μAC7100nFLTC607823–IN+INV+OUTV–12USE NARROW SHORTTRACES FOR MINIMUMCAPACITANCE.Q1RK7002AT116CTR2350kR2450kC1100nFC22.2μFC32.2μFC4100nFR2550kR2650k+INB5VV+INV+3V+INA–INAVOCMR130.5k5VLTC6078V+7–INOUT+INV–5VR4100kC8100nFC1650pFC1750pF123456789101112V+IN+INAV+A–INAVOCMGAIN1RBIASGAIN0(D0)CLKCNTLVOCMCAPLPF1(CS)+OUTA+INBLTC6603–OUTA–INBSERLPF0(SCLK)V+DCLK IOSDIGNDSDO+OUTB–OUTB6603 F06242322212019181716151413C1850pFC1950pF+OUTA–OUTA

C1510nF+OUTB–OUTB

SPI INTERFACEVREFVCC7VOUTSDOSDISCKLTC2621-1CLRCS/LDGNDLDAC1234510SDISCLKCS5VC91μFDATA FORMAT

DATA IS SHIFTED FROM MOSI (MASTER OUT, SLAVE IN) THRU LTC6603 INTO THE LTC2621.

THE TOTAL PACKET IS 32 BITS. IT STARTS WITH A CONTROL BYTE (0011 XXXX) THEN MSB OF THE DAC,WITH DUMMY BITS AT THE END, 16 BITS (24 BITS TOTAL). THEN 8 BITS TO THE FILTER.D6 & D7 = GAIN, D4 & D5 = LPF, D1 = SHDN. D0 = GEN. PURPOSE OUTPUT.

CLR LOW WILL SET DAC TO MID-SCALE (WITH A –1 VERSION).

HAS ~100ms TC AT START-UP TO RESET TO ZERO SCALE.

Figure 6. Current Controlled Clock Frequency100–10–20GAIN (dB)–30–40–50–60

–70VS = 3VTA = 25°C–80

1k10kVCONTROL

RBIAS

+–100k1MFREQUENCY (Hz)10M6603 F07

fCLK= 247.2MHz • (10k/RBIAS) • (1 – VCONTROL/1.17V)

6603 F08

Figure 7. Frequency Response Controlled by LTC2621-1Figure 8. Voltage Controlled Clock Frequency6603f17元器件交易网www.cecb2b.com

LTC6603APPLICATIONS INFORMATION

than 100k. If the value of RBIAS is too large, the ﬁ lters will not receive a large enough bias current, possibly causing errors due to insufﬁ cient settling. Be sure to obey the absolute maximum speciﬁ cations when driving a clock into CLKIO (Pin 15).Input Common Mode and Differential Voltage RangeThe input signal range extends from zero to the V+IN supply voltage. This input supply can be tied to V+A and V+D, or driven up to 5.5V for increased input signal range. Figure 9 shows the distortion of the ﬁ lter versus common mode input voltage with a 2VP-P differential input signal (V+IN = 5V).–60

HD3, f = 1MHzDISTORTION (dBc)control bits LPF1 and LPF0. The differential input imped-ance is a function of the clock frequency and the control bits LPF1, LPF0, GAIN1 and GAIN0. Table 5 shows the typical input impedances for a clock frequency of 80MHz. These input impedances are all proportional to 1/fCLK, so if the clock frequency were reduced by half to 40MHz, the impedances would be doubled. The typical variation in dynamic input impedance for a given clock frequency is –20% to +35%.Table 5. Differential, Common Mode Input Impedances, fCLK = 80MHzGAIN10000000011111111GAIN00000111100001111LPF10011001100110011LPF00101010101010101Differential Common Mode Input Impedance Input Impedance (kΩ)(kΩ)38162.52.5209.52.52.5105.41.91.95.22.81.61.6402055402055402055402055–70

HD3, f = 200kHz–80

RBIAS = 30.9k, VS = 3V, V+IN = 5.5VLPF1 = 1, BW = 2.5MHz, GAIN = 24dBVOUT = VP-P, TA = 25°C1.52.02.53.03.54.04.5COMMON MODE INPUT VOLTAGE (V)

5.0

–901.0

6603 F09

Figure 9. Distortion vs Common Mode Input Voltage (5V)For best performance, the inputs should be driven dif-ferentially. For single ended signals, connect the unused input to VOCM (Pin 3) or to a quiet DC reference voltage. To achieve the best distortion performance, the input signal should be centered around the DC voltage of the unused input.Refer to the Typical Performance Characteristics section to estimate the distortion for a given input level.Dynamic Input ImpedanceThe unique input sampling structure of the LTC6603 has a dynamic input impedance which depends on the conﬁ guration and the clock frequency. This dynamic input impedance has both a differential component and a common mode component. The common mode input impedance is a function of the clock frequency and the Output Common Mode and Differential Voltage RangeThe output voltage is a fully differential signal with a common mode level equal to the voltage at VOCM. Any of the ﬁ lter outputs may be used as single-ended outputs, although this will degrade the performance. The output voltage range is typically 0.5V to V+A – 0.5V (V+A = 2.7V to 3.6V).The common mode output voltage can be adjusted by overdriving the voltage present on VOCM. To maximize the undistorted peak-to-peak signal swing of the ﬁ lter, the VOCM voltage should be set to V+A/2. Note that the output common mode voltages of the two channels are 6603f18元器件交易网www.cecb2b.com

LTC6603APPLICATIONS INFORMATION

not independent as they are both set by the VOCM pin. Figure 10 illustrates the distortion versus output common mode voltage for a 2VP-P differential input voltage and a common mode input voltage that is equal to mid-supply.–60

RBIAS = 30.9k, VS = 3V,GAIN = 24dB, TA = 25°CSIGNAL FREQUENCY = 200kHzHD3, LPF1 = 0, LPF0 = 1HD2, LPF1 = 0,LPF0 = 1Connecting resistors between each input and V+IN will pull the input common mode voltage up, increasing the input signal swing. The resistance, RPULL-UP, necessary to set the input common mode voltage, VICM, to any desired level can be calculated by󰀂VSUPPLY󰀅

R=R󰀁1󰀆CM󰀃 PULL󰀁UP

V󰀄ICM󰀇

where RCM = 40k•80MHz/fCLK for LPF1=0, LPF0=0 RCM = 20k•80MHz/fCLK for LPF1=0, LPF0=1 RCM = 5k•80MHz/fCLK for LPF1=1For example, if the lowpass cutoff frequency is set to 2.5MHz, 5k resistors connected between each input and V+IN will set the input common mode voltage to mid-supply.Circuit A of Figure 12 is for a ﬁ xed CLK and LPF0, LPF1 setting. If the clock varies or the LPF0, LPF1 setting changes then Circuit B of Figure 12 should be used. Due to the sampled data nature of the ﬁ lter, an anti-aliasing ﬁ lter at the inputs is recommended.The output common mode voltage is equal to the voltage of the VOCM pin. The VOCM pin is biased to one half of the supply voltage by an internal resistive divider (see Block Diagram). To alter the common mode output voltage, VOCM can be driven with an external voltage source or resistor network. If external resistors are used, it is important to note that the internal 2k resistors can vary ±30% (their ratio varies only ±1%). The ﬁ lter outputs can also be AC coupled.The LTC6603 can be interfaced to an A/D converter by pull- gures CLKIO (Pin 15) ing CLKCNTL (Pin 5) to V+D. This conﬁas a clock output, which can be used to drive the clock input of the A/D converter. This allows the A/D converter to be synchronized with the ﬁ lter sampling clock, avoiding “beat frequencies” and simplifying the board layout. Any routing attached to the CLKIO pin should be as short as possible, in order to minimize reﬂ ections.Similarly, the LTC6603 can be interfaced to another LTC6603 in a master/slave conﬁ guration as shown in Figure 13. This 6603f–65DISTORTION (dBc)–70

HD2, LPF1 = 1–75

HD3, LPF1 = 1–80

0.81.01.41.21.61.8COMMON MODE OUTPUT VOLTAGE (V)

6603 F10

Figure 10. Distortion vs Common Mode Output VoltageInterfacing to the LTC6603The input and output common mode voltages of the LTC6603 are independent. The input common mode voltage is set by the signal source if DC coupled, as shown in Figure 11. If the inputs are AC coupled, as shown in Figure 12 (Circuit A), the input common mode voltage will be pulled to ground by an equivalent resistance of RCM, shown in Table 5. This does not affect the ﬁ lter’s performance as long as lter gain the input amplitude is less than 0.5VP-P. At low ﬁsettings, a larger input voltage swing may be desired. VSUPPLYLTC6603V+INV+AV+D+INA–INAVIN++OUTA–OUTAVOUT+VOUT–

0.1μF+–VIN–+–1μFVOCMGNDDC COUPLED INPUT

VIN(COMMON MODE) = (VIN+ + VIN–)/2

VOUT(COMMON MODE) = (VOUT+ + VOUT–)/2 = VSUPPLY/2

6603 F11

Figure 11. DC Coupled Inputs19元器件交易网www.cecb2b.com

LTC6603APPLICATIONS INFORMATION

CIRCUIT A

VSUPPLYVSUPPLYLTC6603V+INV+AV+D+INA+OUTA–OUTAVOUT+VOUT–

0.1μFRPULL-UPRPULL-UPVIN++–0.1μFVIN––INA+–0.1μF1μFVOCMGNDAC COUPLED INPUT

VIN(COMMON MODE) = VOUT(COMMON MODE) = VSUPPLY/2

CIRCUIT B

V+INVSUPPLYV+A0.1μF1.87k0.1μF0.1μFLTC6603V+INV+AV+D+INA–INA+OUTA–OUTAVOUT+VOUT–

1.87k+–VIN+1.87k+–VIN–0.1μF1.87k1μFVOCMGNDAC COUPLED INPUTVIN(COMMON MODE) =

RCM•V+IN2•RCM+1.87k

6603 F12

Figure 12. AC Coupled Inputs3.3VLTC6603MASTERV+INV+AV+D3.3VLTC6603SLAVEV+INV+AV+D+OUTA–OUTA0.1μF0.1μF+VIN1+INA–INACLKCNTLCLKIOGND–VOUT1+–+VIN2+INA–INACLKCNTLCLKIOGND+OUTA–OUTA–VOUT2

+–

6603 F13Figure 13. Two Devices in a Master/Slave Clocking Conﬁ guration6603f20元器件交易网www.cecb2b.com

LTC6603APPLICATIONS INFORMATION

results in four matched ﬁ lter channels, all synchronized to the same clock. The master has its CLKCNTL pin pulled guring its CLKIO pin as an output, while the to V+D, conﬁslave has its CLKCNTL pin pulled to ground, conﬁ guring its CLKIO pin as an input. Note that in order to synchronize the two ﬁ lters, the clock frequency must not be buffered. This requires that the ﬁ lters be close together on the PC board. If the clock is buffered, the ﬁ lters would have matching bandwidths, but would not be synchronized.Output DriveThe ﬁ lter outputs can drive 1k and/or 50pF loads connected to AC ground with a 0.5V to 2.5V signal (corresponding to a 4VP-P differential signal). For differential loads (loads connected between +OUTA and –OUTA or +OUTB and –OUTB) the outputs can produce a 4VP-P signal across 2k and/or 25pF. For smaller signal amplitudes, the outputs can drive correspondingly larger loads. For larger capacitive loads, an external 50Ω series resistor is recommended for each output.Clock FeedthroughClock feedthrough is deﬁ ned as the RMS value of the clock frequency and its harmonics that are present at the ﬁ lter’s output. The clock feedthrough is measured with +INA and –INA (or +INB, –INB) tied to VOCM and depends on the PC board layout and the power supply decoupling. The clock feedthrough can be reduced with a simple RC post ﬁ lter.Decoupling CapacitorsThe LTC6603 uses sampling techniques, therefore its performance is sensitive to supply noise. 0.1μF ceramic decoupling capacitors must be connected from V+A (Pin 2) and V+D (Pin 16) to ground with leads as short as possible. A ground plane should be used. Noisy signals should be isolated from the ﬁ lter’s input pins. In addition, a 0.1μF decoupling capacitor at Pin 20 is recommended since this pin receives clocked current injection.AliasingAliasing is an inherent phenomenon of sampled data ﬁ lters. Signiﬁ cant aliasing only occurs when the frequency of the input signal approaches the sampling frequency or mul-tiples of the sampling frequency. The ratio of the LTC6603 input sampling frequency to the clock frequency, fCLK, is determined by the state of control bits LPF1 and LPF0. Table 6 shows the possible input sampling frequencies for a clock frequency of 80MHz. The input sampling frequency is proportional to the clock frequency. For example, if the clock frequency is lowered from 80MHz to 40MHz, the input sampling frequency will be lowered by half. Input signals with frequencies near the input sampling frequency will be aliased to the passband of the ﬁ lter and appear at the output unattenuated.Table 6. Input Sampling Frequency (fCLK = 80MHz)LPF10011LPF00101Input Sampling Frequency (MHz)2040160160A simple LC anti-aliasing ﬁ lter is recommended at the ﬁ lter inputs to attenuate frequencies near the input sam-pling frequency that will be aliased to the passband. For example, if the clock frequency is set to 80MHz and the cutoff frequency of the ﬁ lter is set to its maximum (LPF1 = ‘1’), the lowest frequency that would be aliased to the passband would be fCLK – fCUTOFF, i.e. 160MHz – 2.5MHz = 157.5MHz. The LTC6603 ﬁ lter inputs should be driven by a low impedance output (<100Ω).Wideband NoiseThe wideband noise of the ﬁ lter is the RMS value of the device’s output noise spectral density. The wideband noise is nearly independent of the value of the clock frequency and excludes the clock feedthrough. Most of the wideband noise is concentrated in the ﬁ lter passband and cannot be removed with post ﬁ ltering.Power Supply CurrentThe power supply current depends on the state of the lowpass cutoff frequency controls (LPF1, LPF0) and the value of RBIAS. When the LTC6603 is programmed for the middle cutoff frequency (LPF1 = ‘0’, LPF0 = ‘1’), the supply current is reduced by about 23% relative to the supply current for the higher bandwidth setting. Pro-6603f21元器件交易网www.cecb2b.com

LTC6603APPLICATIONS INFORMATION

gramming the LTC6603 for the lowest cutoff frequency (LPF1 = ‘0’, LFP0 = ‘0’) reduces the supply current by about 60%. Power supply current vs. cutoff frequency for various bandwidth settings is shown in the “Typical Performance Characteristics” section. The LTC6603 can be programmed through the serial interface to enter into a low power shutdown mode. The power supply current during shutdown is less than 235μA.Supply Current vs. Noise TradeoffThe passband of the LTC6603 is determined by the master clock frequency (which is set by RBIAS when the internal oscillator is used), LPF1 and LPF0. The LTC6603 is op-timized for use with RBIAS having a value between 200k and 30.9k to set the internal oscillation frequency from 12.36MHz to 80MHz. The lowpass corner frequency is proportional to the clock frequency (internal or external). 100

To extend the ﬁ lter’s operational frequency range, the master clock is divided down before reaching the ﬁ lter. LPF1 and LPF0 set the division ratio of the lowpass clock. Figure 14 shows the possible cutoff frequencies versus fCLK, LPF1 and LPF0. Overlapping frequency ranges allow more than one possible choice of bandwidth settings for some cutoff frequencies. Figure 15 shows supply current as a function of the ﬁ lter cutoff frequency, LPF1 and LPF0. Note that the higher bandwidth setting always gives the minimum supply current for a given cutoff frequency. The input referred integrated noise voltage for a passband gain of 24dB is shown in Table 7. Note that the noise is higher for the higher bandwidth settings. This creates a tradeoff between supply current and noise. For a given cutoff frequency, using the highest possible bandwidth setting gives the minimum supply current at the expense of higher noise.180160SUPPLY CURRENT (mA)LPF1 = 0LPF0 = 0fCLK (MHz)14012010080604020

TA = 25°CVS = 3VCLKCNTL PIN FLOATINGGAIN = 0dBLPF1 = 0LPF0 = 1LPF1 = 0LPF0 = 0LPF1 = 1LPF1 = 1LPF1 = 0LPF0 = 11010k

100k1M

FILTER CUTOFF FREQUENCY (Hz)

10M

6603 F14

010k

100k1M

FILTER CUTOFF FREQUENCY (Hz)

10M

6603 F15

Figure 14. fCLK vs Filter Cutoff FrequenciesFigure 15. Supply Current vs Filter Cutoff FrequencyTable 7. Total Input Referred Integrated Noise Voltage (Passband Gain = 24dB)LPF1001LPF001XNoise Voltage–81dBm–80dBm–76dBm6603f22元器件交易网www.cecb2b.com

LTC6603TYPICAL APPLICATIONS

LTC6603 Parallel Clock Control3V1V+IN2423784R3DIODES INCDMN2004DWKVOCMR2R10.1μF3+INA–INA+INB–INBRBIASVOCMCAPGAIN1GAIN0(D0)GNDGND2V+A16V+D+OUTA–OUTA+OUTBLTC6603–OUTBCLKIOSER1918131215173V123CSSCLKSDIVOUTGNDV+654VCR20.1μFVB0.1μFR10.1μF3VDAC VOUT RANGE 0V TO 2.5V(USING THE LTC2630 INTERNAL REFERENCE)242378431V+IN+INA–INA+INB–INBRBIASVOCMCAPGAIN1GAIN0(D0)GNDGND2V+ALTC6603 SPI Clock Control3V0.116V+D+OUTA–OUTA+OUTBLTC6603–OUTBCLKIOSER1918131215170.1μF0.1μF20222114CLKCNTLSDOSDILPF0(SCLK)LPF1(CS)5111096LTC26308-BIT DAC2022211425CLKCNTLSDOSDILPF0(SCLK)LPF1(CS)51110963VCLK1CLK0LPF1LPF0GAIN1GAIN0

CLK1 CLK0

0 0 RBIAS1 0 1 RBIAS2 1 0 RBIAS3 1 1 RBIAS4 RBIAS1 > RBIAS2 OR RBIAS3RBIAS = 2472 fCLK

RBIAS IN kfCLK in MHz

fCLK1fCLK2fCLK3fCLK4

25CS16603 TA02SCKSDICS26603 TA03

IF R1 = 51.1k and R2 = 78.7k THEN THE fCLK RANGE IS 12.36MHz to 80MHzR1 =

5.282 • 1012

, R2 =5.282 • 10

1.137fCLKHI + fCLKLOfCLKHI – fCLKLO

fCLK=2.472•10

󰀂R1+R2VC󰀅

󰀁󰀃󰀆

󰀄R1•R2VB•R2󰀇

VC RANGE 0V to 2.5V, VB= 1.17VIF VC = 0V THEN fCLK= fCLKHIIF VC = 2.5V THEN fCLK= fCLKLO

DESIGN PROCEDURE

1. CHOOSE fCLK1, fCLK2 AND fCLK3

2. CALCULATE RBIAS1, RBIAS2 AND RBIAS33. CALCULATE R2, R3 AND RBIAS4R • R R3 = BIAS1 BIAS3

RBIAS1 – RBIAS3

RBIAS4 =

R1 • R2 • R3

R1 • (R2 + R3) + R2 • R3R • R

R1 = RBIAS1 R2 = BIAS1 BIAS2

RBIAS1 – RBIAS2

PACKAGE DESCRIPTION

UF Package24-Lead Plastic QFN (4mm × 4mm)(Reference LTC DWG # 05-08-1697)BOTTOM VIEW—EXPOSED PAD

4.00± 0.10(4 SIDES)0.70±0.05PIN 1TOP MARK(NOTE 6)0.75± 0.05R = 0.115TYPPIN 1 NOTCHR = 0.20 TYP OR 0.35× 45° CHAMFER

23240.40± 0.10124.50± 0.052.45± 0.053.10± 0.05(4 SIDES)2.45± 0.10(4-SIDES)PACKAGEOUTLINE0.25±0.050.50 BSCRECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.200 REF0.00– 0.05(UF24) QFN 01050.25± 0.050.50 BSCNOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6603fInformation furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.23元器件交易网www.cecb2b.com

LTC6603TYPICAL APPLICATION

Direct Conversion Demodulator and I and Q Baseband Filter, fCUTOFF =1.92MHz (UTMS WCDMA)5V3V49.9Ω56nH*10pF45EN6VCC7V8VCC1μF0.1μF1000pFGND9CC3.9pFRF IN321IOUT+161556nH*10pFIOUT10pF0.1μF1V+IN242378+INA–INA+INB–INBRBIASVOCM2V+A16V+D+OUTA–OUTA+OUTBLTC6603–OUTBCLKIOSER0.1μF100pF1918131215100pF1749.9Ω56nH*49.9Ω56nH*10pFQOUT10pF49.9Ω56nH*10pF56nH*100pF10pFGNDGNDRFGND5V–ILTC5575OUTQOUT+14–13QOUT56nH*10pF10pF56nH*100pF10pF0.1μF40.2k0.1μF43LOGNDVCC10111220222114255.6pFLO INCAPGAIN1GAIN0(D0)GNDGNDCLKCNTLSDOSDILPFO(SCLK)LPF1(CS)51110963V1000pF3V*COILCRAFT 0603HP

GAIN1GAIN0BASEBANDGAIN CONTROL

6603 TA04

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PART NUMBERDESCRIPTIONLTC®1565-31LTC1566-1LTC1567LTC1568LTC1569-6LTC1569-7LT1994LTC6406LT6600-2.5LT6600-5LT6600-10LT6600-15LT6600-20LTC6601LTC6602LTC6604-2.5LTC6604-5LTC6604-10LTC6604-15650kHz Linear Phase Lowpass FilterLow Noise, 2.3MHz Lowpass FilterVery Low Noise, High Frequency Filter Building BlockVery Low Noise, 4th Order Building BlockLow Power 10-Pole Delay Equalized Elliptic Lowpass10-Pole Delay Equalized Elliptic LowpassLow Distortion, Low Noise Differential Ampliﬁ er/ADC Driver3GHz Low Noise, Rail-to-Rail Input Differential ADC DriverVery Low Noise, Fully Differential Ampliﬁ er and 2.5MHz FilterVery Low Noise, Fully Differential Ampliﬁ er and 5MHz FilterVery Low Noise, Fully Differential Ampliﬁ er and 10MHz FilterVery Low Noise, Fully Differential Ampliﬁ er and 15MHz FilterVery Low Noise, Fully Differential Ampliﬁ er and 20MHz FilterPin-Conﬁ gurable Second Order Filter/DriverDual Baseband Bandpass Filter for UHF RFIDDual Very Low Noise, Differential Amp and 2.5MHz FilterDual Very Low Noise, Differential Amp and 5MHz FilterDual Very Low Noise, Differential Amp and 10MHz FilterDual Very Low Noise, Differential Amp and 15MHz FilterCOMMENTSContinuous Time, SO8 Package, Fully DifferentialContinuous Time, SO8 Package1.4nV/√Hz Op Amp, MSOP Package, Differential OutputsLowpass and Bandpass Filter Designs Up to 10MHz, Differential OutputsfC ≤ 64kHz, One Resistor Sets fC, SO-8 Differential InputsfC ≤ 256kHz, One Resistor Sets fC, SO-8 Differential InputsAdjustable, Low Power, VS = 2.375V to 12.6VLow Noise: 1.6nV/√Hz, Low Power: 18μA86dB S/N with 3V Supply, SO-8 Package82dB S/N with 3V Supply, SO-8 Package82dB S/N with 3V Supply, SO-8 Package76dB S/N with 3V Supply, SO-8 Package76dB S/N with 3V Supply, SO-8 PackagefC 7MHz to 27MHz Fully Differential 4mm × 4mm QFN PackageFully Differential 4mm × 4mm QFN Package86dB S/N with 3V Supply, 4mm × 7mm QFN Package82dB S/N with 3V Supply, 4mm × 7mm QFN Package82dB S/N with 3V Supply, 4mm × 7mm QFN Package76dB S/N with 3V Supply, 4mm × 7mm QFN Package6603f24Linear Technology CorporationLT 0908 • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com© LINEAR TECHNOLOGY CORPORATION 2008

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