元器件交易网www.cecb2b.com TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999D8-Bit ResolutionDIntegral Linearity ErrorDDDDDDDDDPW OR NS PACKAGE†(TOP VIEW)±0.75 LSB Max (25°C)±1 LSB Max (–35°C to 85°C)Differential Linearity Error±0.5 LSB (25°C)±0.75 LSB Max (–35°C to 85°C)Maximum Conversion Rate10 Mega-Samples per Second(MSPS) Min2.7-V to 3.6-V Single-Supply OperationLow Power Consumption...42mWTypat3 VLow Voltage Replacement for CXD1175CommunicationsDigital ImagingVideo ConferencingHigh-Speed Data ConversionOEDGNDD1(LSB)D2D3D4D5D6D7D8(MSB)VDDDCLK1234 567101112242322212019181716151413DGNDREFBREFBSAGNDAGNDANALOG INVDDAREFTREFTSVDDAVDDAVDDDApplications†Also available in tape and reel andordered as the TLV5510INSR.AVAILABLE OPTIONSTA–35°C to 85°CPACKAGETSSOP (PW)TLV5510IPWSOP (NS)TLV5510INS descriptionThe TLV5510 is a CMOS 8-bit resolution semiflash analog-to-digital converter (ADC) with a 2.7-V to 3.6-V singlepower supply and an internal reference voltage source. It converts a wide band analog signal (such as a videosignal) to a digital signal at a sampling rate of dc to 10 MHz.functional block diagramResistorReferenceDividerREFB200 ΩNOMREFTREFBS60 ΩNOMLower SamplingComparators(4 Bit)40 ΩNOMUpper SamplingComparators(4 Bit)ClockGeneratorPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.OELower SamplingComparators(4 Bit)Lower Encoder(4 Bit)Lower DataLatchD1(LSB)D2D3D4AGNDAGNDVDDAREFTSANALOG INLower Encoder(4 Bit)D5Upper DataLatchUpper Encoder(4 Bit)D6D7D8(MSB)CLKCopyright © 1999, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.comSLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER schematics of inputs and outputsEQUIVALENT OF ANALOG INPUTVDDAEQUIVALENT OF EACH DIGITAL INPUTVDDDEQUIVALENT OF EACH DIGITAL OUTPUTVDDD ANALOG INOE, CLKD1–D8AGNDDGNDDGNDTerminal FunctionsTERMINALNAMEAGNDANALOG INCLKDGNDD1–D8OEVDDAVDDDREFBREFBSNO.20, 2119122, 243–10114, 15, 1811, 132322IOIIII/OAnalog groundAnalog inputClock inputDigital groundDigital data out. D1:LSB, D8:MSBOutput enable. When OE = low, data is enabled. When OE = high, D1 – D8 is high impedance.Analog supply voltageDigital supply voltageReference voltage in (bottom)Reference voltage (bottom). When using the internal voltage divider to generate a nominal 2-V reference,this terminal is shorted to the REFB terminal and the REFTS terminal is shorted to the REFT terminal (seeFigure 21).IReference voltage in (top)Reference voltage (top). When using the internal voltage divider to generate a nominal 2-V reference, thisterminal is shorted to the REFT terminal and the REFBS terminal is shorted to the REFB terminal (seeFigure 21).DESCRIPTIONREFTREFTS1716absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage, VDDA, VDDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VReference voltage input range, REFT, REFB, REFBS, REFTS . . . . . . . . . . . . . . . . . . . . . . . . . AGND to VDDAAnalog input voltage range, VI(ANLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to VDDADigital input voltage range, VI(DGTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to VDDDDigital output voltage range, VO(DGTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to VDDDOperating free-air temperature range, TA –35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 85°CStorage temperature range, Tstg –55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999recommended operating conditionsMINSupply voltageReference input voltage (top), REFTReference input voltage (bottom), REFBAnalog input voltage range, VI(ANLG) (see Note 1)High-level input voltage, VIHLow-level input voltage, VILPulse duration, clock high, tw(H)Pulse duration, clock low, tw(L)Clock frequency, f(CLK)Sampling frequency, fsNOTE 1:REFT – REFB ≤ 2.4 V maximumVDDA–AGNDVDDD–DGNDAGND–DGND2.72.7–100REFB+20REFB2.5101010100.6NOM330MAX3.63.6100VDDA–0.3REFT–2REFT0.5UNITVmVVVVVVnsnsMHzMSPSelectrical characteristics at VDDD = VDDA = 3 V, REFT = 2.5 V, REFB = 0.5 V, f(CLK) = 10 MHz, TA = 25°C (unless otherwise noted)digital I/OPARAMETERIIHIILIOHIOLIOZHIOZLHigh-level input currentLow-level input currentHigh-level output currentLow-level output currentHigh-level high-impedance-stateoutput leakage currentLow-level high-impedance-stateoutput leakage currentVDDD = MAX,VDDD = MAX,OE = GND,OE = GND,OE = VDDD,OE = VDDD,TEST CONDITIONS†VIH = VDDDVIL = 0VDDD = MIN,VDDD = MIN,VDDD = MAXVDDD = MINVOH = VDDD–0.5 VVOL = 0.4 VVOH = VDDDVOL = 0–1.62.615µA15MINTYPMAX55UNITµAmA†Conditions marked MIN or MAX are as stated in recommended operating conditions.powerPARAMETERIDDSupply currentTEST CONDITIONS†fsin = 1 MHz sine wave, reference resistor dissipation is separate6MINTYP410MAX1014UNITmAmAIrefReference voltage current∆REF = REFT – REFB = 2 V†Conditions marked MIN or MAX are as stated in recommended operating conditions.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER electrical characteristics at VDDD = VDDA = 3 V, REFT = 2.5 V, REFB = 0.5 V, f(CLK) = 10 MHz,TA = 25°C (unless otherwise noted) (continued)static performancePARAMETERSelf-bias (1), at REFBSelf-bias (1), REFT – REFBSelf-bias (2), at REFTRrefCiReference voltage resistorAnalog input capacitanceIntegralnonlinearity(INL)Integral nonlinearity (INL)Differentialnonlinearity(DNL)Differential nonlinearity (DNL)TEST CONDITIONS†ShortREFBtoREFBSShort REFB to REFBS,Short REFB to AGND,ShortREFTtoREFTSShort REFT to REFTSShort REFT to REFTSMIN0.1.82.25140TYP0.6022.520016±0.3±0.2–18–20–430±0.75±1±0.5±0.75–6820mVmVLSBMAX0.722.43260ΩpFVUNIT Between REFT and REFBVI(ANLG) = 1.5 V + 0.07 VrmsTA = 25°Cf(CLK) = 10 MHz,,VI = 0.5 V to 2.5 VTA = –35°C to 85°Cf(CLK) = 10 MHz,,VI = 0.5 V to 2.5 VTA = 25°CTA = –35°C to 85°CEZSZero-scale error∆REF = REFT – REFB = 2 VEFSFull-scale error∆REF = REFT – REFB = 2 V†Conditions marked MIN or MAX are as stated in recommended operating conditions.operating characteristics at VDDD = VDDA = 3 V, REFT = 2.5 V, REFB = 0.5 V, f(CLK) = 10 MHz, TA = 25°C (unless otherwise noted)PARAMETERfconvBWtd(D)tAJtd(s)tentdisMaximum conversion rateAnaloginputbandwidthAnalog input bandwidthDigital output delay timeAperture jitter timeSampling delay timeEnable time, OE↓ to valid dataDisable time, OE↑ to high impedanceCL = 10 pFCL = 10 pFInputtone=1MHzInput tone = 1 MHzSpuriousfreedynamicrange(SFDR)Spurious free dynamic range (SFDR)Inputtone=14MHzInput tone = 1.4 MHzSNRSignaltonoiseratioSignal-to-noise ratioInputtone=14MHzInput tone = 1.4 MHzTA = 25°CFull rangeTA = 25°CFull rangeTA = 25°CFull rangeTEST CONDITIONSfI = 1-kHz ramp wave form, VI(ANLG) = 0.5 V – 2.5 VAt – 1 dBAt – 3 dBCL ≤ 10 pF (see Note 1 and Figure 1)MIN0.21736183041510414138383837dBdB30TYPMAX10UNITMSPSMHzMHznspsnsnsnsNOTE 2:CL includes probe and jig capacitance.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999PARAMETER MEASUREMENT INFORMATIONtw(H)CLK (Clock)tw(L)ANALOG IN(Input Signal)NN+1N+2N+3N+4D1–D8(Output Data)N–3tpdN–2N–1NN+1Figure 1. I/O Timing DiagramTYPICAL CHARACTERISTICSPOWER DISSIPATIONvsSAMPLING FREQUENCY12TA = 25°CVDDA = 2.7 V,VREFB = 0.5 V,VREFT = 2.5 V,Fclk = 10 MHzGain – dB0–1–2–3–4––62–7–8100TA = 25°CVDDA = 2.7 V,VREFB = 0.5 V,VREFT = 2.5 V,Fclk = 10 MHz101fI – Input Frequency – MHz102ANALOG INPUT BANDWIDTH10Power Dissipation – mW860024681012Sampling Frequency – MHzFigure 2Figure 3POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.comSLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER TYPICAL CHARACTERISTICSSIGNAL-TO-NOISE RATIOvsINPUT FREQUENCY60TA = 25°CVDDA = 3 V,VREFB = 0.5 V,VREFT = 2.5 V,Fclk = 10 MHz 50Signal-To-Noise Ratio – dB40302010000.511.522.53Input Frequency – MHzFigure 4DIFFERENTIAL NONLINEARITYvsSAMPLES(Under Recommended Operating Conditions)0.50.40.30.20.10–0.1–0.2–0.3–0.4–0.5DNL – Differential Nonlinearity – LSB020406080100120Samples140160180200220240253Figure 56POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TYPICAL CHARACTERISTICSEFFECTIVE NUMBER OF BITSvsTEMPERATURE6.5VDDA = 3 V,VREFB = 0.5 V,VREFT = 2.5 V,Fclk = 10 MHz,fsin = 1 MHz6.45Effective Number Of Bits6.46.356.36.25–40–2040020Ambient Temperature – °C6080Figure 6INTEGRAL NONLINEARITYvsSAMPLES(Under Recommended Operating Conditions)0.750.60.50.40.30.20.10–0.1–0.2–0.3–0.4–0.5–0.6–0.75INL – Integral Nonlinearity – LSB020406080100120Samples1401601802002202402Figure 7POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7元器件交易网www.cecb2b.comSLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER TYPICAL CHARACTERISTICSFAST FOURIER TRANSFORMERvsFREQUENCY(Under Recommended Operating Conditions)Fast Fourier Transformer – dB0–20–40–60–80–100–120–140–160–180–200 00.511.522.533.4.55f – Frequency – MHzFigure 8INTEGRAL LINEARITY ERRORvsFREQUENCY1.81.6INL – Integral Linearity – LSB1.41.210.80.60.40.2057151791113fCLK – Frequency – MHz1921TA = –35°CTA = 85°CVDDD = 2.7 V,VDDA = 2.7 V,VREFT = 2.5 V,VREFB = 0.5 V1.81.6DNL – Differential Linearity – LSBTA = 25°C1.41.210.80.60.40.2057151791113fCLK – Frequency – MHz1921TA = 85°CTA = –35°CTA = 25°CVDDD = 2.7 V,VDDA = 2.7 V,VREFT = 2.5 V,VREFB = 0.5 VDIFFERENTIAL LINEARITY ERRORvsFREQUENCYFigure 9Figure 108POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TYPICAL CHARACTERISTICSINTEGRAL LINEARITY ERRORvsFREQUENCY1.81.6INL – Integral Linearity – LSB1.41.210.80.60.40.2057151791113fCLK – Frequency – MHz1921TA = 85°CTA = –35°CVDDD = 3 V,VDDA = 3 V,VREFT = 2.5 V,VREFB = 0.5 VTA = 25°C1.81.6DNL – Differential Linearity – LSB1.41.210.80.60.4TA = –35°C0.2057151791113fCLK – Frequency – MHz1921TA = 85°CTA = 25°CVDDD = 3 V,VDDA = 3 V,VREFT = 2.5 V,VREFB = 0.5 VDIFFERENTIAL LINEARITY ERRORvsFREQUENCYFigure 11INTEGRAL LINEARITY ERRORvsFREQUENCY1.81.6INL – Integral Linearity – LSB1.41.21TA = 25°C0.80.60.4TA = –35°C0.2057151791113fCLK – Frequency – MHz1921TA = 85°CVDDD = 3.3 V,VDDA = 3.3 V,VREFT = 2.5 V,VREFB = 0.5 V1.81.6DNL – Differential Linearity – LSB1.41.210.80.60.40.2057Figure 12DIFFERENTIAL LINEARITY ERRORvsFREQUENCYVDDD = 3.3 V,VDDA = 3.3 V,VREFT = 2.5 V,VREFB = 0.5 VTA = 25°CTA = 85°CTA = –35°C151791113fCLK – Frequency – MHz1921Figure 13Figure 14POST OFFICE BOX 655303 DALLAS, TEXAS 75265•9元器件交易网www.cecb2b.comSLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER TYPICAL CHARACTERISTICSEFFECTIVE NUMBER OF BITSvsINPUT SINEWAVE FREQUENCY8ENOB – Effective Number of Bits – BitsENOB – Effective Number of Bits – BitsVDDD = 2.7 V,VDDA = 2.7 V8VDDD = 3 V,VDDA = 3 V EFFECTIVE NUMBER OF BITSvsINPUT SINEWAVE FREQUENCY7.57.57TA = –35°C6.57TA = –35°C6.5TA = 25°C6TA = 25°C5.5TA = 85°C500.20.40.60.811.21.4f – Input Sinewave Frequency – MHz6TA = 85°C5.5500.20.40.60.811.21.4f – Input Sinewave Frequency – MHzFigure 15EFFECTIVE NUMBER OF BITSvsINPUT SINEWAVE FREQUENCY8ENOB – Effective Number of Bits – BitsVDDD = 3.3 V,VDDA = 3.3 V7.5TA = –35°C7TA = 25°C6.5TA = 85°CFigure 1665.5500.20.40.60.811.21.4f – Input Sinewave Frequency – MHzFigure 1710POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999APPLICATION INFORMATIONThe following notes are design recommendations that should be used with the TLV5510.DExternal analog and digital circuitry should be physically separated and shielded as much as possible toreduce system noise.DRF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation andproduction process. Breadboards should be copper clad for bench evaluation.DSince AGND and DGND are connected internally, the ground lead in must be kept as noise free as possible.A good method to use is twisted-pair cables for the supply lines to minimize noise pickup. An analog anddigital ground plane should be used on PCB layouts when additional logic devices are used. The AGNDand DGND terminals of the device should be tied to the analog ground plane.placed as close as possible to the appropriate device terminals. A ceramic chip capacitor is recommendedfor the 0.01-µF capacitor. Care should be exercised to assure a solid noise-free ground connection for theanalog and digital grounds.DVDDA to AGND and VDDD to DGND should be decoupled with 1-µF and 0.01-µF capacitors, respectively,DVDDA, AGND, and ANALOG IN terminals should be shielded from the higher frequency terminals, CLK andD0–D7. If possible, AGND traces should be placed on both sides of the ANALOG IN traces on the PCB forshielding.should be 10 Ω or less within the analog frequency range of interest.DIn testing or application of the device, the resistance of the driving source connected to the analog inputPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•11元器件交易网www.cecb2b.comSLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER APPLICATION INFORMATIONVDDA3.3 VVDDD3.3 V +C10FB3C3C4C5FB2FB114VDDADVDDDDVDDD1311C8C915VDDA18VDDAREFTSREFT16C617D8D7D6D5D41098763121224DFrom ClampOutputVideo Input(2VPP)C1BufferR1AC7C219ANALOG IND3D2D122232021REFBSREFBAGNDAGNDCLKOEDGNDDGNDOutput EnableClockLOCATIONC1, C3, C4 –C9C2C10FB1, FB2, FB3R1DESCRIPTION0.1 µF Capacitor10 pF Capacitor47 µF CapacitorFerrite bead75 Ω ResistorFigure 18. Application and Test Schematic Using Internal Reference12POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999PRINCIPLES OF OPERATIONfunctional descriptionThe TLV5510 is a semiflash ADC featuring two lower comparator blocks of four bits each.As shown in Figure 19, input voltage VI(1) is sampled with the falling edge of CLK1 to the upper comparatorsblock and the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1)with the rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1)corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the risingedge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. Accordingto the above internal operation described, output data is delayed 2.5 clocks from the analog input voltagesampling point.Input voltage VI(2) is sampled with the falling edge of CLK2. UD(2) is finalized with the rising edge of CLK3, andLD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) is output with the risingedge of CLK5.VI(1)VI(2)VI(3)VI(4)ANALOG IN(Sampling Points)CLK1CLK (Clock)CLK2CLK3CLK4Upper Comparators BlockS(1)C(1)S(2)C(2)S(3)C(3)S(4)C(4)Upper DataUD(0)UD(1)UD(2)UD(3)Lower Reference VoltageRV(0)RV(1)RV(2)RV(3)Lower Comparators Block (A)Lower Data (A)S(1)H(1)C(1)S(3)H(3)C(3)LD(–1)LD(1)Lower Comparators Block (B)H(0)C(0)S(2)H(2)C(2)S(4)H(4)Lower Data (B)LD(–2)LD(0)LD(2) D1–D8 (Data Output)OUT(–2)OUT(–1)OUT(0)OUT(1)Figure 19. Internal Functional Timing DiagramPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•13元器件交易网www.cecb2b.comSLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER PRINCIPLES OF OPERATIONfunctional description (continued) The MSB comparator block converts on the falling edge of each applied clock cycle. The LSB comparator blocksCB-A and CB-B convert on the falling edges of the first and second following clock cycles, respectively. Thetiming diagram of the conversion algorithm is shown in Figure 19.analog input operationThe analog input stage to the TLV5510 is a chopper-stabilized comparator and is equivalently shown below:S2φ1VDDACsS3φ1To Encoder Logicφ2CsS(N)φ1To Encoder LogicCsφ2φ2To Encoder Logicφ2ANALOG INS1Vref(N)φ1Figure 20. External Connections for Using the Internal Reference Resistor DividerFigure 20 depicts the analog input for the TLV5510. The switches shown are controlled by two internal clocks,φ1 and φ2. These are nonoverlapping clocks that are generated from the CLK input. During the sampling period,φ1, S1 is closed and the input signal is applied to one side of the sampling capacitor, Cs. Also during the samplingperiod, S2 through S(N) are closed. This sets the comparator input to approximately 2.5 V. The delta voltageis developed across Cs. During the comparison phase, φ2, S1 is switched to the appropriate reference voltagefor the bit value N, i.e., Vref(N). S2 is opened and Vref(N) – VCs toggles the comparator output to the appropriatedigital 1 or 0. The small resistance values for the switch, S1, and small value of the sampling capacitor combineto produce the wide analog input bandwidth of the TLV5510. The source impedance driving the analog inputof the TLV5510 should be less than 100 Ω across the range of input frequency spectrum.reference inputs – REFB, REFT, REFBS, REFTSThe range of analog inputs that can be converted are determined by REFB and REFT, REFT being themaximum reference voltage and REFB being the minimum reference voltage. The TLV5510 is tested withREFT = 2.5 V or 2 V and REFB = 0.5 V or 0 V producing a 2-V full-scale range. The TLV5510 can operate withREFT – REFB = 2.4 V, but the power dissipation in the reference resistor increases significantly (49 mW at 3.3Vnominally). It is recommended that a 0.1 µF capacitor be attached to REFB and REFT whether using externallyor internally generated voltages.14POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999PRINCIPLES OF OPERATIONinternal reference voltage conversionThree internal resistors allow the device to generate an internal reference voltage. These resistors are broughtout on terminals VDDA, REFTS, REFT, REFB, REFBS, and AGND. Two different bias voltages are possiblewithout the use of external resistors.The internal resistors are provided to develop REFT and REFB as listed in Table 1 (bias option 1) with only twoexternal connections. This is developed with a 3-resistor network connected to VDDA. When using this feature,connect REFT to REFTS and connect REFB to REFBS. For applications where the variance associated withVDDA is acceptable, this internal voltage reference saves space and cost (see Figure 21).A second internal bias option (bias two option) is shown in Figure 22. Using this scheme REFB = AGND andREFT is as shown in Table 1 (bias option 2). These bias voltage options can be used to provide the values listedin the following table.Table 1. Bias Voltage Options for Different VDDABIASOPTIONBIAS OPTIONVDDA2.7 V13 V3.3 V3.6 V2.7 V23 V3.3 V3.6 VBIAS VOLTAGEVREFB0.0.60.660.72AGNDAGNDAGNDAGNDVREFT2.342.602.863.122.252.52.753VREFT – VREFB1.822.22.42.252.52.753To use the internally-generated reference voltage, terminal connections should be made as shown inFigure 21 or Figure 22.VDDA18TLV5510R140 Ω NOMREFTS16170.1 µFREFTREFB23220.1 µFREFBSAGND21R260 Ω NOM2.63 V dcRref200 Ω NOMFigure 21. External Connections Using the Internal Bias One OptionPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•15元器件交易网www.cecb2b.comSLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER PRINCIPLES OF OPERATIONTLV5510R140 Ω NOM16170.1 µFREFTREFB2322REFBSAGND21R260 Ω NOMRref200 Ω NOM VDDA(Analog Supply)REFTS18Figure 22. External Connections for Using the Internal Reference Resistor Dividerfunctional operationThe TLV5510 functions as shown in the Table 2.Table 2. Functional OperationINPUT SIGNALVOLTAGEREFT••••••STEP255••DIGITAL OUTPUT CODEMSB1••LSB1••1••1••1••1••1••1••128127••10••01••01••01••01••01••01••01••REFB00000000016POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999MECHANICAL DATAPW (R-PDSO-G**) 14 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,651480,300,190,10M0,15 NOM4,504,306,606,20Gage Plane0,251A70°–8°0,750,50Seating Plane1,20 MAX0,150,050,10PINS **DIMA MAX83,10145,10165,10206,60247,902,80A MIN2,904,904,906,407,709,6040400/F 01/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-153POST OFFICE BOX 655303 DALLAS, TEXAS 75265•17元器件交易网www.cecb2b.comSLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999TLV55102.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER MECHANICAL DATANS (R-PDSO-G**) 14 PIN SHOWN PLASTIC SMALL-OUTLINE PACKAGEPINS **DIM0,510,358A MAX1410,501610,502012,902415,301,27140,25MA MIN9,909,9012,3014,700,15 NOM5,605,008,207,40Gage Plane1A70°–10°0,251,050,55Seating Plane2,00 MAX0,05 MIN0,104040062/B 2/95NOTES:A.All linear dimensions are in millimeters.B.This drawing is subject to change without notice.C.Body dimensions do not include mold flash or protrusion, not to exceed 0,15.18POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
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