Chapter 1 Introduction of DSP
What is DSP? What are the differences between or among DSP, the General Purpose Processors (GPP) and the Micro Controller Unit (MCU)? Where and how does DSP apply?
This chapter introduces the conception, characteristics, and applications of DSP. There are some discussions in the distinction between or among DSP, GPP and MCU.
The chapter describes how the DSP develops, gives a brief ‗picture‘ of description of the family TI (Texas Instruments) corporation's DSP, and summarizes TMS320x24xx Series of DSP. DSP的介绍
DSP是什么？DSP和通用处理器（GPP）和微控制器单元（MCU）的差异是什么？在哪里和如何DSP应用？
本章介绍的概念，特点，应用DSP。有在DSP之间或区别讨论，GPP和单片机。
本章介绍了如何在DSP开发，给出了一个简短的“图片”家庭的说明（德克萨斯Instruments）公司的DSP，并总结了tms320x24xx系列DSP。
A digital signal processing system is illustrated as Figure 1.1.
ff F Figure1-1 A digital signal processing system
A/D DSP D/A F The fundamental digital signal processing system consists of the following parts :
F —— the analog filter, which is filtering the noise in the analog signals . A/D —— the analog / digital converter, which is converting the analog signal to
the digital signal.
DSPs——the Digital Signal Processors, which is processing, optimizing,
appraising, compressing, recognizing the digital signal.
D/A ——the digital /analog converter, which is converting the digital signal to the
analog signal.
GPP — general purpose processors
MCU—the Micro Controller Unit— is also called Single Chip Computer. DSP —the digital signal processor
The TMS320 family consists of fixed-point, floating-point, and multiprocessor digital
signal processors (DSPs).
The following characteristics make the TMS320 family the ideal choice for a wide range of processing applications:
（1）Very flexible instruction set. （2） Inherent operational flexibility. （3）nnovative parallel architecture. （4）Cost-effectiveness.
（5） C-friendly architecture. DSP -----the Digital Signal Processor is a new subject concerning many kinds of fields, such as the digital signal processing, optimizing of the figure signal, converting, filtering, value appraising, enhancing, compressing and recognizing, etc.
DSPs-----the Digital Signal Processors is a kind of super–fast computer, which has been optimized for the detection, processing and generation of real world signals, such as voice, video, music, etc. in real time.
A digital signal processing system is illustrated as Figure 1.1.
DSP数字信号处理器-----涉及多种领域的一个新课题，如数字信号处理，优化的数字信号，转换，滤波，价值评价，增强，压缩和识别，等等。 ----- DSP数字信号处理器是一种超–最快的电脑，这已为检测的优化，处理与真实世界的信号，如语音，视频，音乐，在真实的时间等。 数字信号处理系统为例，如图1.1。 ff F A/D DSP D/A F Figure1-1 A digital signal processing system
The fundamental digital signal processing system consists of the following parts :
F —— the analog filter, which is filtering the noise in the analog signals . A/D —— the analog / digital converter, which is converting the analog signal to
the digital signal.
DSPs——the Digital Signal Processors, which is processing, optimizing,
appraising, compressing, recognizing the digital signal.
D/A ——the digital /analog converter, which is converting the digital signal to the
analog signal.
基本的数字信号处理系统由以下几个部分组成： F——模拟滤波器，其滤波模拟信号中的噪声。
A / D——模拟/数字转换器，它是将模拟信号转换为数字信号。
数字信号处理器——数字信号处理器，其处理,评价，优化，压缩，数字信号的识别。 D / A——数字/模拟转换器，它是将数字信号转换为模拟信号。
When a real world analog signal, such as voice, music, video, etc. is inputted, the analog filter is filtering the noise in the analog signals at first. And the analog / digital converter is converting the analog signal to the digital signal. Then the Digital Signal Processors is
processing, optimizing, appraising, compressing and recognizing the digital signal. And then the digital /analog converter is converting the digital signal back to analog signal and the analog filter is filtering the noise in the analog signals again. Finally, the analog signal is sent out for applications.
当一个真实世界的模拟信号，如语音，音乐，视频，等。输入的模拟滤波器，首先是在模拟信号的噪声滤波。和模拟/数字转换器将模拟信号转换为数字信号。然后，数字信号处理器处理，评价，优化，压缩和识别的数字信号。然后，数字/模拟转换器将数字信号转换回模拟信号和模拟滤波器的滤波模拟信号的噪音了。最后，模拟信号发送应用程序。
Chapter2 TMS320LF240x CPU Internal Hardware structure
The TMS320FL240X DSP Central Processing Unit (CPU) can perform high-speed arithmetic within a short instruction cycle by means of its highly parallel architecture, which consists of the following elements: · Program controller.
· Central arithmetic logic unit (CALU).
· Auxiliary register arithmetic unit (ARAU). · Memory-mapped registers.
tms320fl240x DSP的中央处理单元（CPU）可以进行高速运算在一个短的指令周期的高度并行的体系结构，包括以下内容： ·程序控制器。
·中央算术逻辑单元（CALU）。 ·辅助寄存器算术单元（ARAU）。 ·内存映射寄存器。
In this chapter, we shall introduce overview of the elements of the CPU. The content of this chapter includes: □ Architecture Summary
□ Memory and I/O Spaces
□ System Configuration and Interrupts □ Programme controls
在本章中，我们将介绍了CPU的元素的概述。这一章的内容包括： □架构概述 □内存和I/O空间
□系统配置和中断 □计划控制
The components of the multiplier unit, shown in Figure 2–2, consists of the following: （1）16×16-bit parallel multiplier.
（2） 16-bit temporary register (TREG). （3） 32-bit product register (PREG).
LT 00H : load the number 5 comes from 0F000000H
; into TREG
MPY 01H :multiply 5 and 6 comes from TREG and
;0F000001H unit, the result 30 is stored into ;PREG when finish the instruction .
SPL 02H ;store the result 30 (the lower 16 bit )
; to the 0F000002H unit.
The block of TMS320x240x central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle.
The components of this block, shown in Figure 2–3, consists of the following: （1） 32-bit central arithmetic logic unit (CALU). （2） 32-bit accumulator (ACC).
（3） 0- to 7-bit left barrel shifter of output_ scale(OSCALE).
Example 2-2. For example, assume that ACC = 0, PREG = 0022 2200h,, We have this program:
LACC #01111h, 8 ;ACC = 00111100h. Load ACC from prescaling
;shifter
APAC ;ACC = 00333300h. Add to ACC the
;product register.
SACL 05H, -8 ; Store the 16 LSBs of the accumulator into 05H WITH
; right shift 8 bits. Now, the content of 05H is 33H.
SACH 06H, -8 ; Store the 16 MSBs of the accumulator into 06H
;with right shift 8 bits; Now, the content of 06H is 33H.
The CPU interrupt registers in the upper level of heirarchy include the following: （1） The interrupt flag register (IFR). （2） The interrupt mask register (IMR).
Chapter 3 TMS320C240X Addressing
and instruction
This chapter describes the F/C240x addressing, assembly language instructions and C language.
Note the MS320LF240x devices, new members of the TMS320C24x, are part of the TMS320C2000 platform of fixed-point DSPs. The 240x devices offer the enhanced TMS320.
DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller.
The F/C240x instruction set is compatible with the C24x instruction set; code written for the C24x can be reassembled to run on the C240x. And the instruction set for the TMS320C24x is identical to that of the TMS320C2xx core.
Detail information, please reference TI information: 《TMS320C1x/C2x/C2xx/C5x Assembly Language Tools User‘s Guide》.
《TMS320C2x/C2xx/C5x Optimizing C Compiler User‘s Guide》. 《TMS320F/C24x DSP Controllers Reference Guide 》 The content this chapter include: §3.1 Addressing Modes
§3.2 Assembly Language Instructions
§3.3 TMS320C2xx C Programming Language
TMS320C240X寻址 和指令
这一章描述了F / C240x寻址,汇编语言指令和C语言。
注意MS320LF240x设备,新成员,属于TMS320C24x TMS320C2000定点dsp平台。 240x设备提供增强的TMS320。 建筑设计C2xx DSP核心CPU为低成本,低功耗,高性能的处理能力。一些先进的外围设备,优化了数字电机和运动控制应用程序,已经集成提供一个真正的单片DSP控制器。
F / C240x指令集兼容C24x的指令集,编写的代码可以组装的C24x C240x上运行的。和指令集的TMS320C24x完全相同的TMS320C2xx核心。
详细信息,请参考信息:《TMS320C1x TI / C2x / C2xx / C5x汇编语言工具用户指南》。 《C2xx / C5x TMS320C2x / C编译器使用手册》。 《TMS320F / C24x DSP控制器参考指南》 本章内容包括: §3.1寻址模式 §3.2汇编语言指令
§3.3 TMS320C2xx C编程语言
§3.1 Addressing Modes
TMS320LF240X have the three basic memory addressing modes used by the C24x
instruction set. The three modes are: (1) Immediate addressing mode. (2) Direct addressing mode . (3) Indirect addressing mode.
When you need to access data memory, you can use the direct or indirect addressing mode. Direct addressing concatenates seven bits of the instruction word with the nine bits of the data-memory page pointer (DP) to form a 16-bit data memory address. Indirect addressing accesses data memory through one of eight 16-bit auxiliary registers.
3.1寻址模式
有三个基本TMS320LF240X内存寻址模式C24x使用的指令集。这三个模式: 直接寻址模式。
直接寻址模式。 间接寻址模式。
当你需要访问数据的内存,你可以使用直接或间接寻址模式。直接寻址连接七位的指令字与九位的数据内存页面指针(DP)形成一个16位的数据内存地址。间接寻址访问数据存储器通过8个16位辅助寄存器。
Example 3–1.
The immediate operand is contained as a part of the RPT instruction word. The instruction:
Example 3-2.
For a example of long-immediate addressing, see a ADD instruction:
Example 3-3.
A routine using Direct Addressing with ADD (Shift of 0 to 15) LDP #2 ;Set data page to 2 (addresses 0100h–017Fh).
ADD 9h,5 ;The contents of data address 0109h are left shifted 5 bits and added to the contents of the accumulator.
Figure 3-6 the result Addressing with ADD for Example 3–3
Example 3-4.
A routine using Indirect Addressing with MPY(Multiply).
MAR *, AR1 ;Load the ARP with 1 to make AR1 the ;current auxiliary register.
LT *+, AR2 ;AR2 is the next auxiliary register. ;Load the TREG with the content of the ;address referenced by AR1, add one to ;the content of AR1, then make AR2 the ;current auxiliary register.
MPY * ;Multiply TREG by content of address ;referenced by AR2.
There are two mainly tools of compiling C language program: ·The TMS320C2xx C compiler package. ·The Code Composer Studio( CCS).
Chapter4 Introduction of
Program Editor and Debug Environment
This chapter shows how to edit the assembly language and the C language program. And the chapter shows a brief description of general software tools development flow and gives a brief description of each tool. For convenience, it also provides an overview of the Code Composer Studio(CCS)c2000 software development process, the components of Code Composer Studio, and the files and variables used by Code Composer Studio. This chapter includes the following topics: □ Development Flow and Tools Overview. □ Design a program.
□ Synopses of Debug Environment and Code Compiler. □ Simple Steps of Debugging a program. □ Head File and Command File.
这一章展示了如何编辑汇编语言和C语言程序。和这一章显示了一个简短的描述一般的软件工具开发流程和简要描述每个工具的。为方便起见,它还提供了一个概述的代码作曲家工作室(CCS)c2000软件开发过程,组件代码作曲家Studio。文件和变量使用代码作曲家工作室。 本章包括以下主题: □开发流程和工具的概述。 □设计程序。
□对照表的调试环境和代码的编译器。 □的简单步骤调试程序。 □头文件和命令文件。
Procedure for Generating Executable file of
An C language program
Generating your a source program into code that the TMS320LF240x can execute is a
multi-step process. You must edit, compile, assemble, and link your source files to create an executable object file. Procedure for generating executable file of an C language program as follow: 1) Step 1
Use any editor to create:
□ An C language program (names ××× .C).
□ A linker command file that defines address (names ×××.camd). 2) Step 2
Compile the C source code program.
generates an An assembly language program (names ××× .ASM) and list file (names ×××.lst) .
3) Step 3
Assemble the program.
generates an object file (names ×××.obj) and list file (names ×××.lst) . 4) Step4
Use the linker to bring together the information in the object file and the command file and create an executable file (names ×××.out in the figure).
If we design some blocks of Model Program, we usually have to finish three files of different kinds of format before debugging:
（1） Assemble Language File. （2） Head File .
（3） Command File.
Example 4-1:
A linker command file for the TMS320F240x. List as follow:
/***********************************************/ /* Sample command file with SECTIONS directive */
/***********************************************/
MEMORY
{ /* Program Memory */
PAGE 0 : VECS: origin = 0h, length = 020h CODE: origin = 020h, length = 0F90h /* Data Memory */
PAGE 1 : RAMB2: origin = 060h, length = 020h RAMB0: origin = 200h, length = 100h RAMB1: origin = 300h, length = 100h }
SECTIONS {
vectors: > 000000h .text: > CODE .data: > RAMB2 .bss: > RAMB0 newvars: > RAMB1 }
1. CPU Registers Window
This window display contents of CPU Registers during Program debugging process. It includes:
□ PC(program counter) □ ACC(accumulator) □ PREG
□ TREG(temporary register)
□ ST0 and ST1(status register) □ RPTC(repeat counter register) □ TOS
□ AR0～AR7(auxiliary register)
□ IMR(interrupt mask register) □ IFR(interrupt flag register)
□ GREG(global memory allocation register).
Chapter5 Digital I/O Module
This chapter introduces the digital input /output (I/O) module of the TMS 320LF240x. The digital I/O ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and shared pin functions are controlled using nine 16-bit registers.
The chapter describes the architecture, functions, and programming of the digital input /output (I/O) module.
The content this chapter includes: □ Summary of digital I/O ports □ Digital I/O ports registers □ Application of I/O port 数字I / O模块
本章介绍了数字输入/输出(I / O)模块的lf240x TMS 320。数字I / O端口模块提供了一个灵活的方法来控制两个专用I / O和共享功能。所有I / O和共享功能均可使用九16位寄存器。 这一章描述了体系结构、功能和编程的数字输入/输出(I / O)模块。 本章内容包括:
□总结数字I / O端口 □数字I / O端口寄存器 □应用程序的I / O端口
The TMS320LF2407 has up to 41 general-purpose, bidirectional, digital I/O(GPIO) pins—most of which are shared between primary functions and I/O. Most I/O pins of the 2407 are shared with other functions. The digital I/O ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and shared pin functions are controlled using nine 16-bit registers. These register are divided into two types:
（1）Output Control Registers—used to control the multiplexer selection that chooses between the primary function of a pin or the general-purpose I/O function. （2）Data and Control Registers—used to control the data and data direction of bidirectional 数字I / O端口概括
TMS320LF2407的有41通用、双向、数字I / O(GPIO)管脚，大多数管脚是被主要功能和I / O之间共享。大多数2407的I / O的管脚被共享于其他功能。数字I / O端口模块提供了一个灵活的方法来控制两个专用I / O和共享功能。所有I / O和共享功能均可使用九16位寄存器。
这些寄存器分为两种类型:
(1)输出控制寄存器用于控制多路复用器的选择,选择的主要功能之间的一个或通用I / O功能。
(2)数据和控制寄存器用于控制数据和数据方向的双向I / O管脚。 I/O pins.
There are three I/O mux control registers: □I/O mux control register A (MCRA), □I/O mux control register B (MCRB), □I/O mux control register C (MCRC).
There are six data and direction control registers in TMS320LF2407: □ PADATDIR. □ PBDATDIR. □ PCDATDIR. □ PDDATDIR. □ PEDATDIR. □ PFDATDIR.
Chapter 6 Event Manager Module (EV)
This chapter describes the 240x Event Manager (EV) module. The EV module provides a broad range of functions and features that are particularly useful in motion control and motor control applications.
This chapter describes the architecture, functions, and all registers of the Event Manager (EV) module.
The content this chapter includes:
□ Overview the event manager modules (EVA, EVB)
□ General-Purpose (GP) Timers □ Compare Units □ PWM Circuits □ Capture Units
□ Quadrature circuit 事件管理器模块(EV) 这一章描述了240 x事件管理器(EV)模块。电动汽车模块提供了广泛的功能和特性,是特别有用的在运动控制和运动控制应用程序。
这一章描述了体系结构、功能、和所有的寄存器的事件管理器(EV)模块。 本章内容包括:
□概述事件管理器模块(EVA,EVB) □通用(GP)计时器 □比较单位 □PWM电路 □捕获单元 □正交电路
The TMS320LF240x devices include two event manager modules:
(1) event managers A (EVA); (2) event managers B( EVB).
Each event-manager modules include the same units in follows:
□ Two general-purpose (GP) timers, □ Three full-compare/PWM units, □ Three capture units,
□ Two quadrature-encoder pulse (QEP) circuits.
However, these two event manager modules are the same functionality, while names differ with EVA and EVB. Table 6-1 shows the features and functionality available for the event-manager modules and highlights EVA nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however, module/signal names would differ.
概述了事件管理器模块(EVA,EVB)
设备包括两个事件的TMS320LF240x管理模块: 事件管理(EVA); 事件管理B(EVB)。
每个事件管理器模块包括相同的单位如下: 两个通用(GP)定时器, 三全比较/ PWM单元, 三个捕获单元,
两个正交编码器脉冲(QEP)电路。
然而,这两个事件管理器模块是相同的功能,而与EVA和EVB名字不同。表1显示了可用的特性和功能的事件管理器模块和凸显了EVA命名法。
事件管理A和B有相同的外围寄存器集与EVA起始于7400 h和EVB起始于7500 h。这个段落在这一节中描述了函数的GP计时器,比较单元,捕获单元,使用EVA命名法,这些段落是适用于EVB的功能。然而,模块/信号名称会有所不同。
Table6-1. Module and Signal Names for EVA and EVB
EV interrupt events are organized into three groups:
(1) EV interrupt groups A. (2) EV interrupt groups B. (3) EV interrupt groups C.
In each event manager modules (EVA and EVB ),there are two GP timers:
(1) The GP timer 1 and 2 for EVA; (2) The GP timer 3 and 4 for EVB.
Figure 6–29 shows a PWM circuit functional block diagram.
Figure 6-29. PWM Circuits Block Diagram
The PWM circuits includes the following functional units: （1）Asymmetric/Symmetric Waveform Generator. （2） Programmable Dead-Band Unit. （3） Output logic.
（4） SV PWM state machine.
Capture units enable logging of transitions on capture input pins. There are three capture units: Capture Units 1, 2, and 3 and each is associated with a capture input pin. Each capture unit can choose GP timer 2 or 1 as its time base. The value of GP timer 2 or 1 is captured and stored in the corresponding 2-level-deep FIFO stack when a specified transition is detected on a capture input pin (CAPx). Figure 6-37 shows a block diagram of a capture unit.
Figure 6-37. Capture Units Block Diagram
Capture units have the following features:
（1）One 16-bit capture control register, CAPCON (RW). （2）One 16-bit capture FIFO status register, CAPFIFO. （3）election of GP timer 1 or 2 as the time base.
（4）Three 16-bit 2-level-deep FIFO stacks, one for each capture unit.
（5）hree Schmitt-triggered capture input pins, CAP1, CAP2, and CAP3, one input pin for each capture unit. (All inputs are synchronized with the device/ PU clock: in order for a transition to be captured, the input must hold at its current level to meet the two rising edges of the device clock. Input pins CAP1 and CAP2 can also be used as QEP inputs to QEP circuit).
（6）User-specified transition (rising edge, falling edge, or both edges) detection. （7）Three maskable interrupt flags, one for each capture unit.
Chapter7
Analog-to-Digital Converter (ADC)
_This chapter describes the analog-to-digital converter (ADC) of the TMS 320LF240x,
includes a list of features, explains the clock prescaler, and provides register descriptions. The content this chapter include: □ Features of ADC □ ADC Overview
□ ADC CLOCK PRESCALE □ CALIBRATION MODE □ Self-test mode
□ ADC MODULE REGISTERs □ ADC Conversion Clock Period □ ADC Example of transition 模拟-数字转换器(ADC)
这一章描述了模拟-数字转换器(ADC)的TMS 320 lf240x,包括一系列的特性,解释了时钟预定标器,并提供寄存器描述。 本章内容包括: □ADC的特点 □ADC概述
□ADC时钟预分频 □校准模式 □自测模式
□ADC模块寄存器 □ADC转换时钟周期 □ADC的例子的过渡
The ADC sequencer of 2407A consists of two independent 8-state sequencers: SEQ1 and SEQ2.
four trigger sources for start-of-conversion (SOC) sequence: (a) S/W – software immediate start.
(b) EVA – multiple event sources within EVA. (c) EVB –multiple event sources within EVB. (d) Ext – External pin (ADCSOC).
§7-1 Features of ADC
A simplified functional block diagram of the ADC module is shown in Figure 7-1 and
Figure 7-2. The ADC module consists of a 10-bit ADC with a built-in sample-and-hold (S/H) circuit. The Features of the ADC module of TMS320LF2407A include: (1) 10-bit ADC core with built-in Sample and Hold (S/H). (2) Fast conversion time (S/H + Conversion) of 375 ns.
(3) Sixteen (16) multiplexed analog inputs (ADCIN0 – ADCIN15). (4)Autosequencing capability – up to 16 ―autoconversions‖ in a single session. Each conversion session can be programmed to select any one of the 16 input channels.
(5) Two independent 8-state sequencers (SEQ1 and SEQ2) that can be operated individually in dual-sequencer mode or cascaded into one large 16-state sequencer (SEQ) in cascaded mode.
(6) Four Sequencing Control Registers (CHSELSEQn) that determine the sequence of analog channels that are taken up for conversion in a given sequencing mode.
(7) Sixteen (individually addressable) result registers to store the converted values (RESULT0 – RESULT15). The digital value of the input analog voltage is derived by:
一个简化的功能块图的ADC模块如图7 - 1和图7 - 2。ADC模块包括一个10位ADC与一个内置的取样保持的(S / H)电路。ADC模块的功能的TMS320LF2407A包括: (1)10位ADC核心内置取样维持(S / H)。 (2)快速转换时间(S / H +转换)375 ns。
(3)16(16)多路模拟输入(ADCIN0 - ADCIN15)。 (4)Autosequencing能力-
16“autoconversions”在一个会话。 每个转换会话可以通过编程选择任意一个输入通道的16。
(5)两个独立的8状态测序仪(SEQ1和SEQ2),可以单独操作在双重音序器模式或串联成一个大的16个州音序器(SEQ)在级联模式。
(6)四个测序控制寄存器(CHSELSEQn),确定序列的模拟通道,是用作转换在一个给定的序列模式。
(7)16(单独寻址)结果寄存器来存储转换后的值(RESULT0 - RESULT15)。数字值的输入模拟电压中:
(8) Multiple trigger sources for start-of-conversion (SOC) sequence. – S/W – software immediate start.
– EVA – Event manager A (multiple event sources within EVA). – EVB – Event manager B (multiple event sources within EVB). – Ext – External pin (ADCSOC).
(9) Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS _ Sequencer can operate in start/stop mode, allowing multiple timesequenced triggers to synchronize conversions.
(10)EVA and EVB can independently trigger SEQ1 and SEQ2, respectively. (This is applicable for dual-sequencer mode only.)
(11) Sample-and-hold acquisition time window has separate prescale control. (12)Calibration mode. (13) Self-test.
(8)多个触发源开始的转换(SOC)序列。 - S / W -软件立即开始。
EVA-事件管理器一个(多个事件源在EVB)。 ——EVB -事件经理B(多个事件源在EVB)。 - Ext -外部销(ADCSOC)。
(9)灵活的中断控制允许中断请求在每个结束的序列(EOS)或其他EOS _音序器可以操作在启动/停止模式,允许多个timesequenced触发同步转换。
(10)EVA和EVB能独立触发SEQ1和SEQ2,分别。(这是只适用于双音序器模式。) (11)取样保持的采集时间窗口有单独的预分频控制。 (12)校准模式。 (13)自测。
Chapter 8
Serial Peripheral Interface (SPI) Module
This chapter introduces the serial peripheral interface (SPI) mode of the TMS 320LF240x. The serial peripheral interface (SPI) is a high-speed synchronous serial input/ output (I/O)
port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the DSP controller and external peripherals or another controller. Typical applications include external I/O or peripheral expansion via devices such as shift registers, display drivers, and analog-to-digital converters (ADCs).The chapter describes the architecture, functions, registers, and programming of the serial peripheral interface (SPI). The content of this chapter include: 串行外围接口(SPI)模块
本章介绍了串行外围接口(SPI)模式的lf240x TMS 320。 串行外围接口(SPI)是一种高速同步串行输入/输出(I / O)端口,允许一个串行比特流的程序长度(一个16位)被转移的设备在设定位传输速率。SPI通常用于DSP控制器之间的通信和外围设备或另一个控制器。典型的应用包括外部I / O或外围扩张等设备通过移位寄存器、显示驱动程序,模拟数字转换器(adc)。这一章描述了体系结构、功能设计、寄存器、和编程的串行外围接口(SPI)。 本章的内容包括 □ SPI Description □ SPI Operation
□SPI Module Registers
□ SPI Operation-Mode Initialization Examples □SPI的描述 □SPI操作 □SPI模块的寄存器 □SPI操作模式初始化实例
§8.1 SPI Mode Features
FL 2407 devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate.
Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor.
Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi device communications are supported by the master/slave operation of the SPI. SPI模式特征
高度层2407设备有四线串行外围接口(SPI)模块。SPI高速、同步串行I / O端口,允许一个串行比特流的程序长度(一个16位)被转移的设备在一个可编程的位传输速率。 通常,SPI用于DSP控制器之间的通信和外围设备或另一个处理器。
典型的应用包括外部I / O或外围扩张等设备通过移位寄存器、显示驱动程序,adc。多设备通信支持主/从操作的SPI。
The SPI module features include: （1）Four external pins:
□ SPISOMI: SPI slave-output/master-input pin.
□ SPISIMO: SPI slave-input/master-output pin. □ SPISTE: SPI slave transmit-enable pin. □ SPICLK: SPI serial-clock pin.
All four pins can be used as GPIO, if the SPI module is not used. SPI模块的功能包括: (1)四个外部引脚:
□SPISOMI:SPI从输出/主输入引脚。 □SPISIMO:SPI从输入/主输出引脚。 □SPISTE:SPI从传输引脚。 □SPICLK:SPI串行时钟引脚。
（2） Two operational modes: master and slave.
（3）Baud rate: 125 different programmable rates/7.5 Mbps at 30-MHz CPUCLK. （4）Data word length: one to sixteen data bits. （5）Four clocking schemes :
□Falling edge without phase delay: □Falling edge with phase delay: □Rising edge without phase delay: □Rising edge with phase delay:
所有四个引脚可以用作GPIO,如果SPI模块不被使用。 (2)两种操作模式:主和从。
(3)波特率:125不同的可编程利率/ 7.5 Mbps,CPUCLK 30 mhz。 (4)数据字长度:一到十六个数据位。
(5)四个时钟方案(控制时钟极性和时钟相位比特)包括:
□Falling edge without phase delay: SPICLK active high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
□Falling edge with phase delay: SPICLK active high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
□Rising edge without phase delay: SPICLK inactive low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
□Rising edge with phase delay: SPICLK inactive low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
□下降沿没有相位延迟:SPICLK活跃的高。SPICLK信号下降沿时，SPI上传输数据。SPICLK信号的上升沿时， 接收数据
□下降沿与相位延迟:SPICLK活跃的高。SPI传送数据领先SPICLK下降沿一个半周期。SPICLK下降沿时，接收数据。
□上升边没有相位延迟:SPICLK不活跃的低。SPICLK上升沿，SPI进行数据传输。SPICLK下降沿时，接收数据。
□前沿与相位延迟:SPICLK不活跃的低。SPI传输数据领先下降沿一个半周期之前，当SPICLK上升沿时，接收数据。
The three possible methods for data transmission are: （1）Master sends data and slave sends dummy data
（2）Master sends data and slave sends data
（3）Master sends dummy data and slave sends data
（6）Simultaneous receive and transmit operation (transmit function can be disabled in software).
（7）Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
（8）Nine SPI module control registers: Located in control register frame beginning at address 7040h and ending at address 704fh.
All registers in this module are 16-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
register data is in the lower byte (7~0), and the upper byte (15~8) is read as zeros. Writing to the upper byte has no effect.
(6)同时接收和发送操作(传递函数可以在软件中被禁用)。 (7)发射机和接收机操作是通过要么中断驱动或投票算法。
(8)9个SPI模块控制寄存器:位于控制寄存器框架开始地址7040 h和结束地址704F h。 所有的寄存器在这个模块是16位的寄存器,是连接到16位外围总线。当一个寄存器被存取 寄存器的数据是在低字节(7 ~ 0),和上面的字节(15 ~ 8)为零。写到上面的字节没用。 Figure 8-1 shows a block diagram of the SPI in slave mode.
Figure8-1 Serial Peripheral Interface Module Block Diagram
Chapter 9
Serial Communications Interface (SCI) Module
This chapter introduces the serial communications interface (SCI) module of the TMS
320LF240x. The programmable SCI supports asynchronous serial (UART) digital communications between the CPU and other asynchronous peripherals that use the standard NRZ (non-return-to-zero) format. The SCI‘s receiver and transmitter are double buffered, and each has its own separate enable and interrupt bits. Both may be operated independently or simultaneously in the full-duplex mode.
The chapter describes the architecture, functions, and programming of the serial communications interface (SCI) module. 串行通信接口(SCI)模块
本章介绍了串行通信接口(SCI)模块的lf240x TMS 320。可编程的SCI支持异步串行(UART)的数字通信，在CPU和其他异步外设（使用标准的不归零法(非归零)格式）。SCI接收机和发射机是双缓存,每个都有它自己的单独的启用和中断位。既可以独立运行或同时在全双工模式。
这一章描述了体系结构、功能和编程的串行通信接口(SCI)模块。 The content this chapter includes: □ SCI summary
□ Multiprocessor and Asynchronous Communication Modes □ SCI Communication Control Registers □ A typical application of SCI 本章内容包括: □SCI总结
□多处理器和异步通信模式 □SCI通信控制寄存器 □一个典型的应用科学
§9.1 SCI Summary
The 240x devices include a serial communications interface (SCI) module. The SCI
module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupted bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. A 16-bit register, baud-select register, the bit rate is programmable to over 65000 different speeds of data transmission, and all the else registers in this peripheral module are eight bits wide.
240x设备包括一个串行通信接口(SCI)模块。SCI模块支持CPU和其他外围设备之间的数字通信,使用标准的异步非归零(不归零法)格式。SCI接收机和发射机是双缓存,每个都有自己的独立的启用,中断位。既可以独立运行或同时在全双工模式。为确保数据完整性,SCI检查接收的数据,检波、奇偶校验、溢出,并结构错误。一个16位的寄存器,波特选择寄存器,比特率可超过65000个不同的数据传输速度,和所有其他的寄存器在这外围模块是八位宽。
Features of the SCI module include: （1）Two external pins:
□SCITXD: SCI transmit-output pin. □ SCIRXD: SCI receive-input pin.
NOTE: Both pins can be used as GPIO if not used for SCI. The SCI has two multiprocessor protocols:
（1） the idle-line multiprocessor mode. （2） the address-bit multiprocessor mode.
These protocols allow efficient data transfer between multiple processors.
（2） Baud rate can programmable to 64K different rates through a 16-bit baud-select register.
（3）Ranged from76bps to 1875 Kbps at 40-MHz CPUCLK. （4）Data-word format: SCI模块特点包括: (1)两个外部引脚:
□SCITXD:SCI传输输出引脚。 □SCIRXD:SCI接收输入引脚。
注意:两引脚可以用作GPIO如果不是用于SCI。
(2)波特率可以可编程到64 k不同利率，通过16位波特选择寄存器。 (3)从76bps 到1875 Kbps在40 mhz CPUCLK。 (4)数据字格式:
□One start bit.
□ Data-word length programmable from one to eight bits. □ Optional even/odd/no parity bit. □ One or two stop bits. □一个起始位。
□数据字长度可编程从一到八位。 □可选甚至/奇数/不校验位。 □一个或两个停止位。
（5）Four error-detection flags: Parity, overrun, framing, and break detection. （6）Two wake-up multiprocessor modes: Idle-line and address bit waken. （7）Half-duplex or full-duplex operation.
（8） Double-buffered receive and transmit functions.
（9）Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags.
5)四查错标志:奇偶校验,溢出,框架,打破检测。 (6)两个叫醒多处理器模式:空闲线和地址位唤醒。 (7)半双工或全双工操作。 (8)缓冲接收和传输功能。
(9)发射机和接收机操作可以通过中断驱动或调查与状态标志的算法。
□Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty).
□ Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions).
□发射机:TXRDY位(发射机缓冲寄存器准备接收另一个字符)和TX空标志(发射机转变寄存器
是空的)。
□接收机:RXRDY位(接收机缓冲寄存器准备接收另一个字符),BRKDT位(打破条件发生),和RX错误标志(监控四个中断条件)。
（10） Separate enable bits for transmitter and receiver interrupts (except BRKDT). （11） NRZ (non-return-to-zero) format.
（12）Ten SCI module control registers located in the control register frame beginning at address 7050h to 705Fh.
(10)单独启用位发射机和接收机中断(BRKDT除外)。 (11)不归零法(非归零)格式。
(12)10个SCI模块控制寄存器位于控制寄存器结构 开始地址7050h 705fH。
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the register data is in the lower byte (0-7), and the upper byte (8-15) is read as zeros. Writing to the upper byte has no effect. Figure 9-1 shows the SCI module block diagram.
注意:所有注册在这个模块是8位寄存器的16位,是连接到外围总线。当访问一个寄存器,寄存器的数据是在低字节(0 - 7),和上面的字节(8 - 15)解读为零。写作到上面的字节没有影响。图1显示了SCI模块框图。
Figure 9-1 Serial Communications Interface (SCI)
The major elements used in full duplex are shown in Figure 9.1, SCI Block Diagram and include:
（1） A transmitter (TX) and its two major registers (upper half of Figure 9-1):
□ SCITXBUF — transmitter data buffer register. Contains data (loaded by the CPU) to be transmitted.
□ TXSHF register — transmitter shift register. Loads data from register SCITXBUF and shifts data onto the SCITXD pin, one bit at a time.
（2） A receiver (RX) and its two major registers (lower half of Figure 9-1):
□ RXSHF register — receiver shift register. Shifts data in from SCIRXD pin, one bit at a time.
□SCIRXBUF — receiver data buffer register, Contains data to be read by the CPU. Data from a remote processor is loaded into register RXSHF and then into registers SCIRXBUF and SCIRXEMU.
（3） A programmable baud generator.
（4） Data-memory-mapped control and status registers.
The SCI receiver and transmitter can operate either independently or simultaneously. 用于全双工的主要因素如图9.1,SCI框图,包括:
(1)一个发射机(TX)和它的两个主要寄存器(上半部分的图1 - 9): □SCITXBUF——发射机数据缓冲寄存器。包含数据(加载到CPU)传播。
□TXSHF寄存器——发射机移位寄存器。从寄存器SCITXBUF加载数据和转移数据到SCITXD引脚,每次一位。
(2)一个接收器(RX)和它的两个主要寄存器(低一半的图1 - 9):
□RXSHF寄存器-接收移位寄存器。在SCIRXD引脚转移数据,每次一位。 □SCIRXBUF -接收机数据缓冲寄存器,包含被CPU读取的数据。数据从一个远程处理器被加载到寄存器RXSHF然后放入寄存器SCIRXBUF和SCIRXEMU。 (3)一个可编程的波特发生器。
(4)数据映射到内存的控制和状态寄存器。 SCI接收机和发射机可以独立或同时操作。
Chapter 10 CAN Controller Module
This chapter introduces the controller area network (CAN) module available on some members of the 24x/240xA family.
The chapter describes the interface signals, configuration registers, and mailbox RAM of the controller area network (CAN) module. The CAN module is a full-CAN controller designed as a 16-bit peripheral and is fully compliant with the CAN protocol, version 2.0B. The chapter discussed the protocol of Version 2.0 also. The content of this chapter includes: 控制区域控制器模块
本章介绍了控制器区域网络(CAN)模块上可用的一些成员24 x / 240 xa的家庭。
这一章描述了接口信号,配置寄存器,和邮箱内存控制器区域网络(CAN)模块。这个可以模块是一个完全可以设计为一个16位控制器外围和完全符合可以协议,版本2.0 b。这一章讨论了协议的版本2.0。 本章的内容包括:
□ CAN controller module Introduction. □ The Mailboxes of CAN. □ CAN Control Registers. □ CAN Controller Operation.
□ Apply the example of CAN controller. controller area network (CAN)
The DSP CAN controller :
(1)mailbox2 configure as receive mode, (2)mailbox3 configure as transmit mode, (3) all they use stand message frame mode.
10.1.1 CAN Technology Introduction
The CAN is Controller Area Network, It is a net mainly for all kinds of equipment detect and control. CAN was designed by a Germany Company: Bosch. It first for the car detects and control system.
Because the CAN has the special design thought, Good function characteristic with alpine and dependable, the spot anti- interference ability is strong. It is concrete to come speaking, the CAN has as follows characteristics:
这个CAN是控制器区域网络,它是一个网络主要为各种各样的设备检测和控制。CAN设计源自一个德国公司:BOSCH。它首先用于汽车检测和控制系统。
因为CAN有特殊的设计思想,良好的功能特点,反干扰能力强。CAN有如下特点:
（1）It has a simple construction: Only two wires connect with the peripheral equipment, have part contain mistake probe and manage module.
（2）The correspondence method is vivid. It can work in many main ways, the network takes a post idea a node all can at face arbitrarily and every moment and actively the other node of the network to send information, but do not divide the lord from.
（3）It can sends out and receive the data in different way, such as Overall situation broadcast and point to point mode etc.
（4）The information of node on the network can be divided in to different PRI. It can satisfy the
different real time request.
（5）CAN communication frame adopt a short frame, Up to 8 bytes of data, can satisfying usually in the industry control realm control order, work and appearance and test data. At the same time, 8 bytes also no take up the BUS a long time, it ensure a real time communication.
（6）Adopt nondestructive BUS arbitrates technique. When two nodes send out the data to the BUS at the same time, the node have a high initiative can deliver the data insusceptibly, and the other auto stop, this saved consumedly the BUS arbitrates clash time, the network did not paralyzes in a heavy load.
(1)它有一个简单的结构:只有两个导线连接外围设备,有部分包含错误探测和管理模块。 (2)对应的方法是生动的。它可以工作在许多主要的方式,网络需要一个帖子的想法一个节点
均可在任意时刻面对,并积极的网络其他节点发送信息,而不分耶和华。 (3)它可以发送和接收数据采用不同的方式,如全局广播和点对点模式等。 (4)信息网络上的节点可以分为不同的PRI。它可以满足不同的实时要求。
(5)CAN通信帧采用短帧,多达8个字节的数据,可以满足一般工业控制领域的控制命令,工作和外观和测试数据。同时,8个字节也没有占用总线很长时间,它确保实时通信。
(6)采用非破坏性总线仲裁技术。当两个节点发送数据到总线的同时,节点具有较高的主动性可以交付数据无感觉地,其他总线停止,这救了大大的总线仲裁的时间冲突,网络没有麻痹在沉重的负荷。
（7）The direct communication distance of up to 10 Km(below 5 Kbps), and communication speeds of up to 1 Mbps( the distance is the most long for 40 Ms).The node number can amount to 110, the communication medium can be a pair of wringing wires, coaxial cable or optic fiber.
（8）The CAN bus communication interface integrate CAN protocol physics layer with data network layer function, can complete to the correspondence data of handles, including the letter fill the bite , the data piece codes, circulating redundancy check, etc.
（9）The CAN bus adoption CRC examination combine and can provide the homologous mistake handles function, guaranteed the dependable that data correspond by letter.
Because CAN bus has the above some characteristics, control for the industry, the high and dependable and sexual data in inside in system delivered to provide a kind of new solution. its abroad the industry tests the realm there has been the extensive application, now local and many industries control the realm also starts using according to CAN of bus in the spot, the bus in the spot that CAN bus have become to have most the development prospect bus
(7)直接通信距离10公里(低于5 Kbps)和通信速度高达1 Mbps(距离是最渴望40 Ms)。节点数可达110,通信介质可以是双扭线,同轴电缆或光纤。
(8)CAN总线通信接口集成可以协议层网络层物理数据功能,可以完成对通信数据的处理,包括这封信填补咬,数据块编码、循环冗余校验等。
(9)CAN总线采用CRC检查结合,可以提供相应的错误处理函数,保证了可靠的数据对应的字母。
由于CAN总线具有以上特点,控制工业、高可靠和性数据在系统交付给提供了一种新的解决方案。它的国外行业测试领域已经有了广泛的应用,现在地方和许多工业控制领域也开始使用根据可以在现场的总线,总线在现货,CAN总线已成为最有发展前景的总线
Chapter11 Application: Designed Principle of a AC Induction Motor Control system
TMS320F/C240X is a family of DSP, based on a 30 MIPS 16-bit fixed-point DSP core associated with several micro-controller peripherals, such as a Pulse Width Modulation
(PWM) generator and Analog to Digital Converters (ADC).
An important and typical application of TMS320F/C240X is for the Digital Motor Control segment. The target applications for this device are as follows:
TMS320F / C240X是DSP的一个家族,基于30 MIPS 16位定点DSP核心和好几个微控制器外围设备,比如一个脉冲宽度调制(PWM)发生器和模拟数字转换器(ADC)。
一个重要的和典型的应用TMS320F / C240X是为数字电机控制部分。对于这个设备的目标应用程序如下:
□ Appliances (washers, blowers, compressors).
□ HVAC (heating, ventilation and air conditioning).
□Industrial servo drives (Motion control, Power supply inverters, Robotics). □Automotive control (Power steering, Anti-lock brakes, Suspension controls). □电器(洗衣机、鼓风机、压缩机)。 □暖通空调(采暖、通风和空调)。
□工业伺服驱动器(运动控制、电源逆变器、机器人)。 □汽车控制(动力转向,防抱死制动系统、悬架控制)。
This family of DSP controllers is designed with solutions for motor control that guarantees robustness, reliability, low price and high efficiency. However, a powerful processor, such as this controller, can:
这个家族的DSP控制器设计解决方案,保证电动机控制的鲁棒性、可靠性、价格低、效率高。然而,一个强大的处理器,比如这个控制器,可以:
□ favor system cost reduction by an efficient control in all speed ranges implying right dimensioning of power device circuits.
□ perform high-level algorithms due to reduced torque ripple, resulting in lower vibration and longer lifetime.
□ enable a reduction of harmonics using enhanced algorithms, to meet easier requirements and to reduce filters cost.
□ remove speed or position sensors by the implementation of sensorless algorithms.
□ decrease the number of look-up tables which reduces the amount of memory required. □ real-time generation of smooth near-optimal reference profiles and move trajectories, resulting in better-performing.
□ control power switching inverters and generates high-resolution PWM outputs. □ provide single chip control system.
For advanced controls, Those controllers may also perform the following:
□ enable control of multi-variable and complex systems using modern intelligent methods such as neural networks and fuzzy logic.
□perform adaptive control. DSPs have the speed capabilities to concurrently monitor the system and control it. A dynamic control algorithm adapts itself in real time to variations in system behavior.
□provide diagnostic monitoring with FFT of spectrum analysis. By observing the frequency spectrum of mechanical vibrations, failure modes can be predicted in early stages. □系统成本降低的有利高效控制在所有速度范围正确尺寸的暗示功率器件电路。 □执行高级算法由于减少了转矩脉动,从而降低振动和更长的寿命。 □使减少谐波使用增强的算法,以满足需求,减少过滤器容易成本。 □删除速度或位置传感器的无传感器的实现算法。
□减少查表的数量,减少了所需的内存数量。
□实时生成平滑接近参考资料和移动轨迹,导致性能更好。 □控制功率开关逆变器并生成高分辨率的PWM输出。 □提供单片机控制系统。
对先进控制,这些控制器也可以执行以下:
□使多变量复杂系统的控制,使用现代智能方法如神经网络和模糊逻辑。
□进行自适应控制。dsp具有速度功能来同时监控系统和控制它。一个动态控制算法实时调整本身变化的系统行为。
□提供诊断监测与FFT频谱分析。通过观察机械振动的频谱,失效模式可以预测在早期阶段。
Figure11.8 Three-Phase VSI Diagram
Principle:The relationship between the switching variable vector [ a, b, c]t and the line-to-line output voltage vector [ Vab Vbc Vca]t:
Table 11.1 Device On/Off States and Corresponding Outputs of a Three-Phase VSI
TMS320C240X Assembly Language Instructions(88 Instructions) Table 3–4. Accumulator, Arithmetic, and Logic Instructions 1 ABS Absolute Value of Accumulator 2 ADD Add to Accumulator With Shift 3 ADDC Add to Accumulator With Carry
4 ADDS Add to Accumulator With Sign Extension 5 ADDT Add to Accumulator With Shift Specified by T Register 6 AND AND With Accumulator 7 CMPL Complement Accumulator
8 LACC Load Accumulator With Shift
9 LACL Load Low Accumulator and Clear High Accumulator 10 LACT Load Accumulator With Shift Specified by TRegister 11 NEG Negate Accumulator
12 NORM Normalize Contents of Accumulator 13 OR OR With Accumulator 14 ROL Rotate Accumulator Left
16 SACH Store High Accumulator With Shift 17 SACL Store Low Accumulator With Shift 18 SFL Shift Accumulator Left 19 SFR Shift Accumulator Right
20 SUB Subtract From Accumulator With Shift 21 SUBB Subtract From Accumulator With Borrow 22 SUBC Conditional Subtract
23 SUBS Subtract From Low Accumulator With Sign
24 SUBT Subtract From Accumulator With Shift Specified by T Register 25 XOR Exclusive-OR With Accumulator
26 ZALR Zero Low Accumulator, Load High Accumulator With Rounding Table 3–5. Auxiliary Register Instructions
1 ADRK Add to Auxiliary Register Short Immediate 2 BANZ Branch on Auxiliary Register Not Zero 3 CMPR Compare Auxiliary Register With AR0 4 LAR Load Auxiliary Register 5 MAR Modify Auxiliary Register 6 SAR Store Auxiliary Register
7 SBRK Subtract From Auxiliary Register Short Immediate Table 3–6. TREG, PREG, and Multiply Instructions 1 APAC Add P Register to Accumulator 2 LPH Load High P Register 3 LT Load T Register 4 LTA Load T Register and Accumulate Previous Product 5 LTD Load T Register, Store P Register in Accumulator 6 LTP Load T Register, Store P Register in Accumulator 7 LTS Load T Register, Subtract Previous Product the contents from the accumulator same to accumulator.
(1)data send TREG (2)(ACC - shifted (PREG)) send ACC 8 MAC Multiply and Accumulate
9 MACD Multiply and Accumulate With Data Move 10 MPY Multiply
11 MPYA Multiply and Accumulate Previous Product 12 MPYS Multiply and Subtract Previous Product 13 MPYU Multiply Unsigned
14 PAC Load Accumulator With P Register
15 SPAC Subtract P Register From Accumulator 16 SPH Store High P Register 17 SPL Store Low P Register
18 SPM 2-bit constant Set P Register Output Shift Mode 19 SQRA Square and Accumulate Previous Product 20 SQRS Square and Subtract Previous Product Table 3–7. Branch Instructions 1 B Branch Unconditionally
2 BACC Branch to Address Specified by Accumulator 3 BANZ Branch on Auxiliary Register Not Zero 4 BCND Branch Conditionally 5 CALA Call Subroutine Indirect 6 CALL Call Subroutine 7 CC Call Conditionally 8 INTR Soft Interrupt 9 NMI Nonmaskable Interrupt 10 RET Return From Subroutine 11 RETC Return Conditionally 12 TRAP Software Interrupt Table 3–8. Control Instructions 1 BIT Test Bit
2 BITT Test Bit Specified by T Register 3 CLRC Clear Control Bit 4 IDLE Idle Until Interrupt
5 LDP Load Data Memory Page Pointer 6 LST Load Status Register 7 NOP No Operation
8 POP POP Top of Stack to Low Accumulator
1.DSP---digital signal processing[数字信号处理］
2.DSPS---digital signal processors[数字信号处理蕊片] 3.数字信号处理的种类 ①通用处理器（GPP）
②单片机/微控制器［Single Chip Computer/ Micro Controller Unit（MCU）］ ③数字信号处理器(DSP )
1.加法器的步骤（第二章 P42）
The steps in the implementation of a typical ALU instruction
The steps occur in the implementation of a typical ALU instruction: (1) Data is fetched from memory on the data bus,
(2) Data is passed through the prescaler and the ALU, where the arithmetic is performed. (3) The result is moved into the ACC. 在一个典型的ALU指令的实施步骤
步骤发生在一个典型的ALU指令的执行： （1）数据从内存中读取数据总线上的，
（2）数据通过预分频器和运算，在算法执行。 （3）结果是移入ACC
2.完成一个C语言从编程到执行的四个步骤。
Procedure for Generating Executable file of An C language program
Generating your a source program into code that the TMS320LF240x can execute is a multi-step process. You must edit, compile, assemble, and link your source files to create an executable object file. Procedure for generating executable file of an C language program as follow: 1) Step 1
Use any editor to create:
An C language program (names ××× .C).
A linker command file that defines address (names ×××.camd). 2) Step 2
Compile the C source code program.
generates an An assembly language program (names ××× .ASM) and list file (names ×××.lst) . 3) Step 3
Assemble the program.
generates an object file (names ×××.obj) and list file (names ×××.lst) . 4) Step4
Use the linker to bring together the information in the object file and the command file and create an executable file (names ×××.out in the figure). 生成的可执行文件的程序 一个C语言程序
生成您的源程序代码，使之在TMS320LF240x系列可以执行，是一个多步骤的过程。您必须
编辑，编译，汇编，和你的源文件的链接，来创建一个可执行的目标文件。用于生成一个C语言程序的可执行文件的程序如下： 1）步骤1
使用任何编辑器来创建：
一个C语言程序（名字×××。C）。
一个连接命令文件中定义的地址（姓名×××。CAMD）。 2）步骤2
编译的C源代码程序。
生成一个汇编语言程序（名字×××。ASM） 和列表文件（名称×××。LST）。 3）步骤3 汇编程序。
生成一个目标文件（名称×××。obj） 和列表文件（名称×××。LST）。 4）步骤4
使用连接器使目标文件中的信息和命令文件连在一起，创建一个可执行文件（名称×××。在图）。
3.编一个命令程序（给出地址范围）P142 Example4-1 Example 4-1:
A linker command file for the TMS320F240x. List as follow:
/***********************************************/ /* Sample command file with SECTIONS directive */
/***********************************************/
MEMORY
{ /* Program Memory */
PAGE 0 : VECS: origin = 0h, length = 020h CODE: origin = 020h, length = 0F90h /* Data Memory */
PAGE 1 : RAMB2: origin = 060h, length = 020h RAMB0: origin = 200h, length = 100h RAMB1: origin = 300h, length = 100h }
SECTIONS {
vectors: > 000000h .text: > CODE .data: > RAMB2 .bss: > RAMB0
newvars: > RAMB1 }
4.PWM（P236）
5.P386
Figure11.8 Three-Phase VSI Diagram
Device On/Off States and Corresponding Outputs of a Three-Phase VSI
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