专利名称：Bus system发明人：松永 敏幸申请号：JP2015189795申请日：20150928公开号：JP6600518B2公开日：20191030
摘要：When a first dummy master device receives a signal indicating that valid data ispresent, in place of a first master device, the first dummy master device outputs a signalindicating that signal reception is possible. A selector is configured to connect one of thefirst master device and the first dummy master device to a bus. A system controller isconfigured to cause only a master device to which a failure occurs to be reset, among aplurality of master devices. A selector control circuit is configured to control the selectorto connect the first dummy master device to the bus when the first master device is in afailure state.
申请人：ルネサスエレクトロニクス株式会社
地址：東京都江東区豊洲三丁目２番２４号
国籍：JP
代理人：特許業務法人深見特許事務所
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