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MT88E39

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CMOSMT88E39CallingNumberIdentiﬁcationCircuitAdvance Information(CNIC1.1)Features••1200 baud Bell 202 and CCITT V.23 FrequencyShift Keying (FSK) demodulationCompatible with Bellcore GR-30-CORE,SR-TSV-002476, TIA/EIA-716 andETSI 300 778-1High input sensitivityDual mode 3-wire data interface (Serial FSKdata stream or MT88E43 compatible 1 bytebuffer)Internal gain adjustable ampliﬁerCarrier detect status outputUses 3.5795 MHz crystal or ceramicresonator3 to 5V±10% supply voltageLow power CMOS with power down modeDirect pin to pin replacement of MT8841 andMT88E41DS5035ISSUE 3November 1998Ordering InformationMT88E39AS16 Pin SOIC-40 to +85°C••DescriptionThe MT88E39 Calling Number Identiﬁcation Circuit(CNIC1.1) is a CMOS integrated circuit whichprovides an interface to calling line informationdelivery services that utilize 1200 baud Bell 202 orCCITT V.23 FSK data transmission schemes. TheMT88E39 receives and demodulates the FSK signaland outputs the data into a simple dual mode 3-wireserial interface which eliminates the need for anUART.The MT88E39 is Bellcore, ETSI and NTT compatibleand can operate in 3V and 5V applications. It is a pinto pin replacement of the MT8841 and MT88E41 byoperating in the MT88E41 FSK interface mode(mode 0) when placed in a MT88E41 socket. Newdesigns may also choose the MT88E43 compatibleinterface (mode 1) where the microcontroller readsthe FSK byte from a 1 byte buffer.••••••Applications•Global (North America, Japan, Europe) FSKbased CID (Calling Identity Delivery) / CLIP(Calling Line Identity Presentation)Feature phones, adjunct boxesFAX machinesTelephone answering machinesComputer Telephony Integration (CTI)Battery powered applications•••••GSIN-IN+-+ReceiveBandpassFilterFSKDemodulatorData and TimingRecoveryDATADRDCLKCAPVRefBiasGeneratorCarrierDetectorCDClockGeneratorto othercircuitsPWDNOSC1OSC2VSSVDDMODEICFigure 1 - Functional Block Diagram5-1MT88E39Advance InformationIN+IN-GSVRefCAPOSC1OSC2VSS1234567816151413121110916 PIN SOICVDDIC**MODE*PWDNCDDRDATADCLK* Was IC1 in MT88E41** Was IC2 in MT88E41Figure 2 - Pin ConnectionsPin DescriptionPin #1234567NameIN+IN-GSVRefCAPNon-inverting Op-Amp (Input).Inverting Op-Amp (Input).Gain Select (Output). Gives access to op-amp output for connection of feedback resistor.Voltage Reference (Output).Nominally VDD/2. This is used to bias the op-amp inputs.Capacitor. Connect a 0.1µF capacitor to VSS.DescriptionOSC1Oscillator (Input).Crystal connection. This pin can be driven directly from an externalclocking source.OSC2Oscillator (Output).Crystal connection. When OSC1 is driven by an external clock, this pinshould be left open.VSSPower supply ground.DCLK3-wire FSK Interface: Data Clock (CMOS Output/Schmitt Input). In mode 0 (MT88E41compatible mode - when the MODE pin is logic low) this is a CMOS output which denotes thenominal mid-point of a FSK data bit.In mode 1 (when the MODE pin is logic high) this is a Schmitt trigger input used to shift theFSK data byte out to the DATA pin.DATA3-wire FSK Interface: Data (CMOS Output).In mode 0 (MT88E41 compatible mode - whenthe MODE pin is logic low) the FSK serial bit stream is output to DATA as demodulated. Markfrequency corresponds to logical 1. Space frequency corresponds to logical 0.In mode 1 (when the MODE pin is logic high) the start and stop bits are stripped off and onlythe data byte is stored in a 1 byte buffer. At the end of each word signalled by theDR pin, themicrocontroller should shift the byte out to DATA pin by applying 8 read pulses at the DCLK pin.3-wire FSK Interface: Data Ready (Open Drain/CMOS Output). Active low. In mode 0(MT88E41 compatible mode - when the MODE pin is logic low) this is an open drain output. Inmode 1 (when the MODE pin is logic high) this is a CMOS output.This pin denotes the end of a word. Typically,DR is used to interrupt the microcontroller. It isnormally hi-Z or high (modes 0 and 1 respectively) and goes low for half a bit time at the end ofa word. But in mode 1 if DCLK begins duringDR low, the ﬁrst rising edge of the DCLK inputwill returnDR to high. This feature allows an interrupt requested byDR to be cleared uponreading the ﬁrst DATA bit.Carrier Detect (Open Drain/CMOS Output). Active low. In mode 0 (MT88E41 compatiblemode - when the MODE pin is logic low) this is an open drain output. In mode 1 (when theMODE pin is logic high) this is a CMOS output.A logic low indicates that a carrier has been present for a speciﬁed time on the line. A timehysteresis is provided to allow for momentary discontinuity of carrier. The demodulated FSKdata is inhibited until the carrier has been detected.1011DR12CD13PWDNPower Down (Schmitt Input). Active high. Powers down the device including the inputop-amp and the oscillator. Must be low for operation.5-2Advance InformationPin DescriptionPin #14NameDescriptionMT88E39MODEMode select (Input). This pin selects the 3-wire FSK interface mode. To select mode 0(MT88E41 compatible mode) this pin should be logic low. To select mode 1 this pin should belogic high.Because this pin is already connected to Vss in ’E41 applications, the MT88E39 can replacethe ’E41 without any circuit or software change.ICVDDInternal Connection. Internal connection. Leave open circuit. In MT88E41, this was IC2which was also left open in the application circuit.Positive power supply voltage.The MT88E39 provides an interface to the Caller IDphysical layer. It bandpass ﬁlters and demodulatesthe 1200 baud FSK signal. It also provides aconvenient interface to extract the demodulated FSKdata. Although the main application of the MT88E39is Caller ID, it can also be used wherever 1200 baudBell 202 and/or CCITT V.23 FSK reception isrequired.3 to 5V operationThe MT88E39 can operate from 5.5V down to 2.7V,but the FSK reject level will change with Vdd. In abattery powered CPE, the FSK accept level willbecome lower as the batteries are run down. If theCPE is designed for 4.5V, the accept level will belowered when the batteries drain to 3V. In NorthAmerica there is a requirement for rejecting FSKsignals which are below 3 mVrms when data is notpreceded by ringing, such as VMWI (Visual MessageWaiting Indicator) applications. When the batteriesare drained, the CPE will not meet the reject level.For on-hook Caller ID, there is no reject level and theCPE will meet all requirements.Input ConﬁgurationThe input arrangement of the MT88E39 provides anoperational ampliﬁer, as well as a bias source (VRef)which is used to bias the inputs at VDD/2. Provision ismade for connection of a feedback resistor to theop-amp output (GS) for adjustment of gain.Figure 3 shows the necessary connections for adifferential input conﬁguration. In a single-endedconﬁguration, the input pins are connected as shownin Figure 4.1516Functional DescriptionThe MT88E39 is a FSK demodulator compatible withFSK based Caller ID services around the world, suchas in North America, France, Germany, and Japan.Caller ID is the generic term for a group of servicesoffered by telephone operating companies wherebyinformation about the calling party is delivered to thesubscriber. In the FSK based methods, theinformation is modulated in either Bell 202 (in NorthAmerica) or CCITT V.23 (in Europe) FSK format andtransmitted at 1200 baud from the serving end ofﬁceto the subscriber’s terminal.In North America, Caller ID uses the voiceband datatransmission interface deﬁned in the Bellcoredocument GR-30-CORE. The terminal or CPE(Customer Premises Equipment) requirements aredeﬁned in Bellcore document SR-TSV-002476.Typical services are CND (Calling Number Delivery),CNAM (Calling Name Delivery), VMWI (VisualMessage Waiting Indicator) and CIDCW (CallingIdentity Delivery on Call Waiting).In on-hook Caller ID, such as CND and CNAM, theinformation is typically transmitted from the endofﬁce before the subscriber picks up the phone.There are various methods such as between the ﬁrstand second rings (North America), between anabbreviated ring and the ﬁrst true ring (Japan,France and Germany). On-hook Caller ID can alsooccur without ringing for services such as VMWI.The MT88E39 is suitable for these forms of alerting.In off-hook Caller ID, such as CIDCW, informationabout a new calling party is sent to the subscriberwho is already engaged in a call. Bellcore’s methoduses a special dual tone known as CAS (CPEAlerting Signal) which should be detected by theCPE. After the CPE has acknowledged with a DTMFdigit, the end ofﬁce will send the FSK data. TheMT88E39 is suitable for receiving the FSK data but aseparate CAS detector is required.5-3MT88E39C1R1IN+IN-C2R4R5GSR3R2VRefDIFFERENTIAL INPUT AMPLIFIERC1 = C2MT88E39R1 = R4R3 = (R2 x R5) / (R2 + R5)For unity gain, R5 = R1VOLTAGE GAININPUT IMPEDANCE(AVdiff) = R5/R1(ZINdiff) = 2R12 + (1/ωC)2Figure 3 - Differential Input ConﬁgurationIN+CRIN-INRFGSVOLTAGE GAINVRef(AV) = RF / RINMT88E39Figure 4 - Single-Ended InputConﬁguration3-wire FSK Data InterfaceThe MT88E39 provides a powerful dual mode 3-wireinterface so that the 8-bit data words in thedemodulated FSK bit stream can be extractedwithout the need either for an external UART or forthe microcontroller to perform the UART function insoftware. The interface is speciﬁcally designed forthe 1200 baud rate and is comprised of the DATA,DCLK (data clock) andDR (data ready) pins. Twomodes (0 and 1) are selectable via control of thedevice’s MODE pin. In mode 0 the FSK bit stream isoutput as demodulated. In mode 1 the FSK data byteis store in a 1 byte buffer. Note that in mode 0DRandCD are open drain outputs; in mode 1 they areCMOS outputs. DCLK is an output in mode 0, aninput in mode 1.5-4Advance InformationMode 0This mode is selected when the MODE pin is low. Itis the MT88E41 compatible mode where the FSKdata stream is output as demodulated. Since theMODE pin was IC1 in MT88E41 and connected toVss, the MT88E39 will work in mode 0 when placedin a MT88E41 socket.In this mode, the MT88E39 receives the FSK signal,demodulates it, and outputs the data directly to theDATA pin (see Figure 11). For each received stopand start bit sequence, the MT88E39 outputs a ﬁxedfrequency clock string of 8 pulses at the DCLK pin.Each DCLK rising edge occurs in the nominal centreof a data bit. DCLK is not generated for the stop andstart bits. Consequently, DCLK will clock only validdata into a peripheral device such as a serial toparallel shift register or a microcontroller. TheMT88E39 also outputs an end of word pulse (DataReady) on theDR pin, which indicates the receptionof every 10-bit word (counting the start and stop bits)sent from the end ofﬁce.DR can be used to interrupta microcontroller or cause a serial to parallelconverter to parallel load its data into amicrocontroller. The mode 0 DATA pin can also beconnected to a personal computer’s serialcommunication port after converting from CMOS toRS-232 voltage levels.Mode 1This mode is selected when the MODE pin is high. Inthis mode, the microcontroller supplies read pulsesat the DCLK pin (which is now an input) to shift the8-bit data words out of the MT88E39, onto the DATApin. The MT88E39 assertsDR to denote the wordboundary and indicate to the microprocessor that anew word has become available (see Figure 12).Internal to the MT88E39, the demodulated data bitsare sampled and stored. The start and stop bits arestripped off. After the 8th bit, the data byte is parallelloaded into an 8 bit shift register andDR goes low.The shift register’s contents are shifted out to theDATA pin on the supplied DCLK’s rising edge in theorder they were received.If DCLK begins whileDR is low,DR will return to highupon the first DCLK. This feature allows theassociated interrupt to be cleared by the first readpulse. OtherwiseDR is low for half a nominal bit time(1/2400 sec). After the last bit has been read,additional DCLKs are ignored.Note that in both modes, the 3-pin interface may alsooutput data generated by speech or other voicebandAdvance Informationsignals. The user may choose to ignore theseoutputs when FSK data is not expected, or force theMT88E39 into its power down mode.Power Down ModeFor applications requiring reduced powerconsumption, the MT88E39 can be forced into powerdown when it is not needed. This is done by pullingthe PWDN pin high. In power down mode, theoscillator, op-amp and internal circuitry are alldisabled and the MT88E39 will not react to the inputsignal.DR andCDare at high impedance or at logichigh (modes 0 and 1 respectively). In mode 0, DATAand DCLK are at logic high. The MT88E39 can beawakened for reception of the FSK signal by pullingthe PWDN pin low.Carrier DetectThe carrier detector provides an indication of thepresence of a signal in the FSK frequency band. Itdetects the presence of a signal of sufﬁcientamplitude at the output of the FSK bandpass ﬁlter.The signal is qualiﬁed by a digital algorithm beforetheCD output is set low to indicate carrier detection.A 10ms hysteresis is provided to allow formomentary signal drop out onceCD has beenactivated.CD is released when there is no activity atthe FSK bandpass ﬁlter output for 10 ms.WhenCD is inactive (high), the raw output of thedemodulator is ignored by the data timing recoverycircuit (see Figure 1). In mode 0, the DATA pin isforced high. No DCLK orDR signal is generated. Inmode 1, the internal shift register is not updated andnoDR is generated. If DCLK is clocked (in mode 1),DATA is undeﬁned.Note that signals such as CAS, speech and DTMFtones also lie in the FSK frequency band and thecarrier detector may be activated by these signals.They will be demodulated and presented as data. Toavoid false data, the PWDN pin should be used todisable the FSK demodulator when no FSK signal isexpected.Ringing, on the other hand, does not pose a problemas it is ignored by the carrier detector.Crystal OscillatorThe MT88E39 uses either a 3.5795MHz ceramicresonator or crystal oscillator as the master timingsource.MT88E39The crystal speciﬁcation is as follows:Frequency:3.5795 MHzFrequency tolerance:±0.2%(-40°C+85°C)Resonance mode:ParallelLoad capacitance:18 pFMaximum series resistance:150 ohmsMaximum drive level (mW):2 mWe.g. CTS MP036SMT88E39MT88E39MT88E39OSC1OSC2OSC1OSC2OSC1OSC2to the3.5795 MHznext MT88E39(For 5V application only)Figure 5 - Common Crystal ConnectionFor 5V applications any number of MT88E39 devicescan be connected as shown in Figure 5 such thatonly one crystal is required. The connection betweenOSC2 and OSC1 can be DC coupled as shown, orthe OSC1 input on all devices can be driven from aCMOS buffer (dc coupled) with the OSC2 outputs leftunconnected.VRef and CAP InputsVequal to VRef is the output of a low impedance voltage sourceDD/2 and is used to bias the input op-amp.A 0.1µF capacitor is required between CAP and Vto suppress noise on VSSRef.ApplicationsTable 1 shows the Bellcore and ETSI FSK signalcharacteristics. The application circuit in Figure 6 willmeet these requirements.For 5V designs the input op-amp should be set tounity gain to meet the Bellcore requirements and-2.5 dB gain for ETSI requirements.As supply voltage (VDD) is decreased, the FSKdetect threshold will be lowered. Therefore fordesigns operating at other than 5V nominal voltage,to meet the FSK reject level requirement the gain ofthe op-amp should be reduced accordingly.For 3V designs the gain settings for Bellcore andETSI should be -3dB and -5.5dB respectively.5-5MT88E39For applications requiring detection of lower FSKsignal level, the input op-amp may be conﬁgured toprovide adequate gain. However, too much gain willcause noise tolerance to fail the TIA requirementsbecause the FSK signal will be clipped at GS whenthe single tone noise is added.Advance InformationVddTIPVddR2MT88E39IN+VDDICMODEPWDNCDDRDATADCLKVdd100nF 20% C1R1D1D2VddVddR9*1RING C2R3D3D4R4R5R7R6IN-GSVRefCAPR8*1100nF 20%D5D7D6D81N5231BOSC1XtalOSC2VSS100nF10%50V(FSK interface mode 0 selected)Vdd= To microcontroller= From microcontroller200K5%4K5%(Ring Detect)10nFTo microcontroller330nF R1010%250VMotorola4N25Note:*1R8 and R9 not required when FSK interface mode 1 is selected.Unless stated otherwise, resistors are 1%, 0.1 Watt; capacitors are 5%, 6.3VD1, D2, D3, D4 = diodes, 1N4003 or 1N4148 or equivalentD5, D6, D7, D8 = bridge rectiﬁer diodes, 1N914Xtal = 3.5795 MHz, +/-0.2%R8 = R9 = 100K, 20%R10 = 12K1, 1W5, 5%, Fusible resistorR2 = R4 = 34KFor 1000Vrms, 60Hz isolation from Tip to Earth and Ring to Earth:R1 = R3 =430K, 0.5W, 5%, 475V minimum. e.g. IRC Type GS-3C1 = C2 =2n2, 1332V minimumIf the 1000Vrms is met by other means, then this circuit has to meet FCC part 68 Type B Ringing:R1 = R3 =432K, 0.1W, 1%, 56V minimumC1 = C2 =2n2, 212V minimumExample of component values for Vdd = 5V +/- 10%For Bellcore applications, set input gain = 0dB:R5 = 53K6R6 = 60K4R7 = 4KExample of component values for Vdd = 3V +/- 10%For Bellcore applications, set input gain = -3 dB:R5 = 44K2R6 = 51K1R7 = 332KFor ETSI applications, set input gain = -2.5dB:R5 = 53K6R6 = 63K4R7 = 348KFor ETSI applications, set input gain = -5.5dB:R5 = 44K2R6 = 53K6R7 = 249KFigure 6 - Application Circuit5-6Advance InformationNorth America: Bellcore*11200 Hz +/- 1%2200 Hz +/- 1%-36.20 to -4.23 dBm*3(12 to 476 mVrms)-48.23 dBm (3 mVrms) (VMWI only)1200 baud +/- 1%-6 to +10 dBSingle tone (f):-18 dB (f<=60Hz)-12 dB (60=3200Hz)0 dBMT88E39Europe: ETSI*21300 Hz +/- 1.5%2100 Hz +/- 1.5%-33.78 to -5.78 dBm(-36 to -8 dBV*4)*5-47.78 dBm (-50 dBV)1200 baud +/- 1%-6 to +6 dBParameterMark (logical 1) frequencySpace (logical 0) frequencyReceived signal levelReject signal levelTransmission rateTwistSignal to noise ratio>= 25 db(300 to 3400 Hz)MT88E39 FSK input gain for Vdd=5V +/-10%-2.5 dBTable 1 - FSK signal characteristics speciﬁed by some standard bodiesNotes:*1:Recommended by TIA/EIA-716. Bellcore has agreed to the values and will incorporate them into its future standards.*2:ETS 300 778-1 (On-hook) Sep 97, ETS 300 778-2 (Off-hook) Jan 97.*3:dBm = Decibels above or below a reference power of 1mW into 600 ohms. 0dBm=0.7746Vrms.*4:dBV = Decibels above or below a reference voltage of 1Vrms. 0dBV=1Vrms.*5:On-hook signal range. The Off-hook signal levels are inside this range: -30.78 to -7.78 dBm.VddInterrupt Source 1INT1(open drain)R1 can be opened andD1 shorted if themicrocontroller does notread theINT1 pin.Interrupt Source 2INT2(CMOS)R1D1VddMicrocontrollerINT (input)VddMT88E39DR(Mode 0: Open Drain)(Mode 1: CMOSR2 *Input Port Bit*R2 can be omitted if mode 1 is selectedFigure 7 - Application Circuit (multiple interrupt source)5-7MT88E39Absolute Maximum Ratings* -Voltages are with respect to VSS unless otherwise stated.Parameter12345DC Power Supply Voltage VDD to VSSVoltage on any pinCurrent at any pin (except VDD and VSS)Storage TemperaturePackage Power DissipationSymbolVDDVPII/OTSTPD-65Min-0.3-0.3Advance InformationMax6VDD+0.3±10+150500UnitsVVmA°CmW*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.Recommended Operating Conditions- Voltages are with respect to ground (VSS) unless otherwise statedCharacteristics1234DC Power Supply VoltageClock FrequencyTolerance on Clock FrequencyOperating TemperatureSymVDDfOSC∆fc-40Min2.73.5795TypMax5.5UnitsVMHzTest Conditions±0.2+85%°CDC Electrical Characteristics†Characteristics12SUPPLYDR,CD,DATA,DCLKSym IDDQ IDDMinTyp*0.11.21.9Max152.03.0UnitsµAmAmAmAmATestConditionsNotes* 1Notes* 2Standby Supply CurrentOperating Supply CurrentVDD=3.0V, 25oCVDD=5.0V, 25oCSink CurrentSource current DATA DCLK (in mode 0)DR,CD (in mode 1)Output hi-Z current (in mode 0)Schmitt Input High ThresholdSchmitt Input Low ThresholdSchmitt HysteresisCMOS Input High VoltageCMOS Input Low VoltageInput CurrentOutput VoltageOutput Resistance34IOLIOH2.50.8VOL=0.1VDDVOH=0.9VDD56DR,CDIOZVT+VT-VHYSVIHVILIINVRefRRef0.5*VDD- 0.10.48*VDD0.28*VDD0.20.7*VDDVSS100.68*VDD0.48*VDDµAVVVVOZ=VSS to VDD71011PWDN,DCLK(inmode 1)MODEPWDN,DCLK,MODEVRefVDD0.3*VDD100.5*VDD + 0.12VµAVkΩVSS ≤ VIN≤ VDDNo Load†DC Electrical Characteristics are over recommended operating conditions unless otherwise stated.*Typical ﬁgures are at 25°C and are for design aid only.Notes*:1.PWDN=Vdd. FSK input = 0 mVrms. Digital inputs at either Vdd or Vss. No current drawn from output pins.2.PWDN=Vss. FSK input = 0 mVrms. With no current drawn from Vref, OSC2 and all digital pins.5-8Advance InformationElectrical Characteristics† - Gain Setting AmpliﬁerCharacteristics1234567Input Leakage CurrentInput ResistanceInput Offset VoltagePower Supply Rejection RatioCommon Mode RejectionDC Open Loop Voltage GainUnity Gain BandwidthOutput Voltage SwingCapacitive Load (GS)SymIINRinVOSPSRRCMRRAVOLfCVOCLRLVCM1001.0VDD-1.0MT88E39MinTyp‡Max1UnitsµAMΩTest ConditionsVSS ≤ VIN ≤ VDD5253030400.20.5VDD-0.7mVdBdBdBMHzVpFkΩVLoad≥ 100kΩ1kHz ripple on VDDVCMmin≤ VIN ≤ VCMmax5010Resistive Load (GS)11Common Mode Voltage Range†Electrical characteristics are over recommended operating conditions, unless otherwise stated.‡Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.AC Electrical Characteristics† - FSKCharacteristics1Input Detection LevelSymMin-37.78-4010118811882178120012002200Typ‡Max-1.78-4631121212122222UnitsdBm1, 2, 3, 4dBVmVrmsbaudHzHzHzHzdB10dB6Notes*2Input Baud Rate3Input Frequency DetectionBell 202 1 (Mark)Bell 202 0 (Space)CCITT V.23 1 (Mark)CCITT V.23 0 (Space)4Input Noise Tolerance20 log(signal)noise5Twist=20 log(VMark)VSpace}6 BELL 202 Frequencies}6CCITT V.23 Frequencies1280.513001319.52068.521002131.5SNR20-63, 4, 5†AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.‡Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Notes*:1.dBm = Decibels above or below a reference power of 1mW into 600Ω. 0dBm=0.7746Vrms.2.dBV = Decibels above or below a reference voltage of 1Vrms. 0dBV=1Vrms.3.Input op-amp conﬁgured to 0dB gain at Vdd=5V+/-10%, -3dB at Vdd=3V+/-10%.4.Mark and Space frequencies have the same amplitude.5.Band limited random noise (200-3400Hz). Present when FSK signal present.6.OSC1 at 3.5795 MHz±0.2%.5-9MT88E39AC Electrical Characteristics† - TimingCharacteristics12345CDPWDNOSC1Advance InformationSym tPUtPDtIALtIAHMinTyp‡Max50Unitsmsµsmsmsms1Notes*Power-up timePower-down timeInput FSK toCDlow delayInput FSK toCDhigh delayHysteresis1001010100025†AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.‡Typical ﬁgures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.Notes*:1.The device will stop functioning within this time, but more time may be required to reach IDDQ.AC Electrical Characteristics† - 3-Wire FSK Interface Timing (Mode 0)Characteristics123456710111213DRDCLKDRDCLKDATADCLKDATASymMin1188Typ‡12001Max12125200200Unitsbpsmsnsnsµsµs331, 6Notes*RateInput FSK to DATA delayRise timeFall timeDATA to DCLK delayDCLK to DATA delayFrequencyHigh timeLow timeDCLK toDR delayRise timeFall timeLow timetCHtCLtCRDtRRtFFtRLtIDDtRtFtDCDtCDD661200.441111161202.8411161205.2417417417102001, 2, 5, 61, 2, 5, 62222442Hzµsµsµsµsnsµs41117†AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.‡Typical ﬁgures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.Notes*:1.FSK input data at 1200±12 baud.2.OSC1 at 3.5795 MHz±0.2%.3.10k to VSS, 50pF to VSS.4.10k to VDD, 50pF to VSS.5.Function of signal condition.6.For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations.AC Electrical Characteristics† - 3-Wire FSK Interface Timing (Mode 1)Characteristics12345DCLKDRDCLKSymfDCLK1MinTyp‡Max1UnitsMHz%nsnsnsNotes*See Fig. 12FrequencyDuty CycleRise TimeDCLK low setup time toDRDCLK low hold time toDR30tDDStDDH50050070100See Fig. 12See Fig. 12†AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.‡Typical ﬁgures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.5-10Advance InformationtDCDtCDDtFMT88E39tRDATADCLKtCLtRtCHtFFigure 8 - DATA and DCLK Output Timing (Mode 0)tFFDRtRLtRRFigure 9 -DR Output Timing (Mode 0)2 secTIP/RINGFirst Ring500ms(min)channel seizureMark statechecksumInput FSKData200ms(min)SecondRingPWDNtPUtPDOSC2CD *tIALtIAHDATAHigh (Input Idle)High (Input Idle)DCLK(mode 0)DR ** with pull-up resistor in mode 0Figure 10 - Input and Output Timing (Bellcore CND Service)5-11MT88E39startstopTIP/RINGb7tIDDstartDATAb7stopb0b1b2b3b4b5b6b7stopstart10b0b1b2b3b4b5b6b7startstop10Advance Informationstartstopb0b1b2b3b4b5b6b710b0b1b2startb0b1b2b3b4b5b6b7stopb0b1b2DCLKtCRDDR ** with external pull-up resistorFigure 11 - Serial Data Interface Timing (Mode 0)DemodulatedData(Internal Signal)word N7stopstart012word N+13456tRL7stopDR (Data Ready)CMOStDDSOutputtDDHDCLK (Data Clock)*Schmitt InputDATA Output67󰃀1/fDCLK1󰃁0123word N45670word N-1*The DCLK input must be low before and afterDR falling edge󰃀DCLK clearsDR󰃁DCLK does not clearDR, soDR is low for maximum time (1/2 bit time)Figure 12 - Serial Data Interface Timing (Mode 1)5-12Package OutlinesPin 1EALHCeD4 mils (lead coplanarity)Notes:1) Not to scale2) Dimensions in inches3) (Dimensions in millimeters)4)A & B Maximum dimensions include allowable mold flashBLA1DIMAA1BCDEeHL16-PinMin0.093(2.35)0.004(0.10)0.013(0.33)0.009(0.231)0.398(10.1)0.291(7.40)18-PinMin0.093(2.35)0.004(0.10)0.013(0.33)0.009(0.231)0.447(11.35)0.291(7.40)20-PinMin0.093(2.35)0.004(0.10)0.013(0.33)0.009(0.231)0.496(12.60)0.291(7.40)24-PinMin0.093(2.35)0.004(0.10)0.013(0.33)0.009(0.231)0.5985(15.2)0.291(7.40)Max0.104(2.65)0.012(0.30)0.020(0.51)0.013(0.318)0.614(15.6)0.299(7.40)Min28-PinMax0.104(2.65)0.012(0.30)0.020(0.51)0.013(0.318)0.7125(18.1)0.299(7.40)Max0.104(2.65)0.012(0.30)0.020(0.51)0.013(0.318)0.413(10.5)0.299(7.40)Max0.104(2.65)0.012(0.30)0.030(0.51)0.013(0.318)0.4625(11.75)0.299(7.40)Max0.104(2.65)0.012(0.30)0.020(0.51)0.013(0.318)0.512(13.00)0.299(7.40)0.093(2.35)0.004(0.10)0.013(0.33)0.009(0.231)0.697(17.7)0.291(7.40)0.050 BSC(1.27 BSC)0.394(10.00)0.016(0.40)0.419(10.65)0.050(1.27)0.050 BSC(1.27 BSC)0.394(10.00)0.016(0.40)0.419(10.65)0.050(1.27)0.050 BSC(1.27 BSC)0.394(10.00)0.016(0.40)0.419(10.65)0.050(1.27)0.050 BSC(1.27 BSC)0.394(10.00)0.016(0.40)0.419(10.65)0.050(1.27)0.050 BSC(1.27 BSC)0.394(10.00)0.016(0.40)0.419(10.65)0.050(1.27)Lead SOIC Package - S SufﬁxNOTES:1. Controlling dimensions in parenthesis ( ) are in millimeters.2. Converted inch dimensions are not necessarily exact.General-7http://www.mitelsemi.com

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