HCTL-2020资料

HCTL-2000

Quadrature Decoder/Counter Interface ICs

Data Sheet

HCTL-2000, HCTL-2016, HCTL-2020

Description

The HCTL-2000, 2016, 2020 are CMOS ICs thatperform the quadrature decoder, counter, and businterface function. The HCTL-20XX family is designedto improve system performance in digital closed loopmotion control systems and digital data input systems.It does this by shifting time intensive quadraturedecoder functions to a cost effective hardware solution.The entire HCTL-20XX family consists of a 4xquadrature decoder, a binary up/down state counter,and an 8-bit bus interface.

Features

•Interfaces encoder to microprocessor•14 MHz clock operation•Full 4X decode

•High noise immunity: Schmitt Trigger inputs digital noisefilter

•12 or 16-bit binary up/down counter•Latched outputs

•8-Bit tristate interface

•8, 12, or 16-bit operating modes

•Quadrature decoder output signals, up/down and count•Cascade output signals, up/down and count•Substantially reduced system software

Applications

•Interface quadrature incremental encoders tomicroprocessors

•Interface digital potentiometers to digital data input buses

Note: Avago Technologies encoders are notrecommended for use in safety critical applications.Eg. ABS braking systems, power steering, life supportsystems and critical care medical equipment. Pleasecontact sales representative if more clarification isneeded.

Devices

Part NumberHCTL-2000HCTL-2016HCTL-2020

Description

12-bit counter. 14 MHz clock operation.

All features of the HCTL-2000. 16-bit counter.

All features of the HCTL-2016. Quadrature decoder outputsignals. Cascade output signals.

Package Drawing

AAB

ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL-20XX family ICs.

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The use of Schmitt-triggeredCMOS inputs and input noisefilters allows reliable operation innoisy environments. The HCTL-2000 contains a 12-bit counter.The HCTL-2016 and 2020contain a 16-bit counter. TheHCTL-2020 also containsquadrature decoder output

signals and cascade signals foruse with many standard counterICs. The HCTL-20XX familyprovides LSTTL compatible tri-state output buffers. Operation isspecified for a temperature rangefrom -40 to +85°C at clockfrequencies up to 14 MHz.

Package Dimensions

19.05 ± 0.25(0.750 ± 0.010)

25.91 ± 0.25(1.02 ± 0.010)

15°

1.52 ± 0.13(0.060 ± 0.005)

9.40 (0.370)

15°

Operating Characteristics

Table 1. Absolute Maximum Ratings

(All voltages below are referenced to VSS)

ParameterDC Supply VoltageInput VoltageStorage TemperatureOperating Temperature

SymbolVDDVINTSTA[1]

Limits-0.3 to +5.5-0.3 to VDD +0.3-40 to +125-40 to +85

UnitsVV°C°C

Table 2. Recommended Operating Conditions

ParameterDC Supply VoltageAmbient Temperature

SymbolVDDTA[1]

Limits+4.5 to +5.5-40 to +85

UnitsV°C

2

Table 3. DC Characteristics VDD = 5 V ± 5%; TA = -40 to 85°CSymbolVIL[2]VIH[2]VT+VT-VHIINVOH[2]VOL[2]IOZIDDCINCOUT

Parameter

Low-Level Input VoltageHigh-Level Input VoltageSchmitt-Trigger Positive-Going Threshold

Schmitt-Trigger Negative-Going Threshold

Schmitt-Trigger HysteresisInput CurrentHigh-Level OutputVoltage

Low-Level OutputVoltage

High-Z Output LeakageCurrent

Quiescent Supply CurrentInput CapacitanceOutput Capacitance

VIN = VSS or VDDIOH -1.6 mAIOL = +4.8 mAVO = VSS or VDD

VIN = VSS or VDD, VO = HiZAny Input[3]Any Output[3]

-101.01.0-102.43.5

3.51.52.014.50.21156

0.4+105+104.0

Condition

Min.

Typ.

Max.1.5

UnitVVVVVµAVVµAµApFpF

Notes:1. Free air.

2. In general, for any VDD between the allowable limits (+4.5 V to +5.5 V), VIL = 0.3 VDD and VIH = 0.7 VDD; typical values areVOH= VDD - 0.5 V @ IOH = -40 µA and VOL = VSS + 0.2 V @ IOL = 1.6 mA.3. Including package capacitance.

Figure 2. Waveform for Positive Clock Related Delays.

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Functional Pin Description

Table 4. Functional Pin DescriptionsSymbolVDDVSSCLKCHACHBPinPin2000/201620201682762010298Power SupplyGroundCLK is a Schmitt-trigger input for the external clock signal.CHA and CHB are Schmitt-trigger inputs which accept the outputsfrom a quadrature encoded source, such as incremental optical shaftencoder. Two channels, A and B, nominally 90 degrees out of phase,are required.This active low Schmitt-trigger input clears the internal positioncounter and the position latch. It also resets the inhibit logic. RST isasynchronous with respect to any other input signals.This CMOS active low input enables the tri-state output buffers. TheOE and SEL inputs are sampled by the internal inhibit logic on thefalling edge of the clock to control the loading of the internal positiondata latch.This CMOS input directly controls which data byte from the positionlatch is enabled into the 8-bit tri-state output buffer. As in OE above,SEL also controls the internal inhibit logic.SEL01CNTDCDRU/D165BYTE SELECTEDHighLowDescriptionRST57OE44SEL33A pulse is presented on this LSTTL-compatible output when thequadrature decoder has detected a state transition.This LSTTL-compatible output allows the user to determine whetherthe IC is counting up or down and is intended to be used with theCNTDCDR and CNTCAS outputs. The proper signal U (high level) or D(low level) will be present before the rising edge of the CNTDCDR andCNTCAS outputs.A pulse is presented on this LSTTL-compatible output when theHCTL-2020 internal counter overflows or underflows. The rising edgeon this waveform may be used to trigger an external counter.These LSTTL-compatible tri-state outputs form an 8-bit output portthrough which the contents of the 12/16-bit position latch may be read in2 sequential bytes. The high byte, containing bits 8-15, is read first (on theHCTL-2000, the most significant 4 bits of this byte are set to 0 internally).The lower byte, bits 0-7, is read second.CNTCAS15D0D1D2D3D4D5D6D7NC115141312111091191817141312116Not connected - this pin should be left floating.4

Switching Characteristics

Table 5. Switching Characteristics Min/Max specifications at VDD = 5.0 ± 5%, TA = -40 to + 85°C.

Symbol Description

1234567101112131415161718192021

tCLKtCHHtCD[1]tODEtODZtSDVtCLHtSS[2]tOS[2]tSH[2]tOH[2]tRSTtDCDtDSDtDODtUDDtCHDtCLDtUDHtUDCStUDCH

Clock period

Pulse width, clock high

Delay time, rising edge of clock to valid, updated countinformation on D0-7

Delay time, OE fall to valid data

Delay time, OE rise to Hi-Z state on D0-7

Delay time, SEL valid to stable, selected data byte(delay to High Byte = delay to Low Byte)Pulse width, clock low

Setup time, SEL before clock fallSetup time, OE before clock fallHold time, SEL after clock fallHold time, OE after clock fallPulse width, RST low

Hold time, last position count stable on D0-7 after clock riseHold time, last data byte stable after next SEL state changeHold time, data byte stable after OE riseDelay time, U/D valid after clock rise

Delay time, CNTDCDR or CNTCAS high after clock riseDelay time, CNTDCDR or CNTCAS low after clock fallHold time, U/D stable after clock rise

Setup time, U/D valid before CNTDCDR or CNTCAS riseHold time, U/D stable after CNTDCDR or CNTCAS rise

10tCLK-45tCLK-4528202000281055

45

Min.7028

656065Max.

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

Notes:

1. tCD specification and waveform assume latch not inhibited.

2. tSS, tOS, tSH, tOH only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setupand hold times do not need to be observed.

Figure 3. Tri-State Output Timing.

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Figure 5. Decoder, Cascade Output Timing (HCTL-2020 only).

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A block diagram of the HCTL-20XX family is shown in Figure 6.The operation of each majorfunction is described in thefollowing sections.

Figure 6. Simplified Logic Diagram.

Digital Noise Filter

The digital noise filter section isresponsible for rejecting noise onthe incoming quadrature signals.The input section uses twotechniques to implementimproved noise rejection.Schmitt-trigger inputs and athree-clock-cycle delay filtercombine to reject low level noiseand large, short duration noisespikes that typically occur inmotor system applications. Bothcommon mode and differentialmode noise are rejected. The userbenefits from these techniques byimproved integrity of the data in

the counter. False counts

triggered by noise are avoided.Figure 7 shows the simplifiedschematic of the input section.The signals are first passed

through a Schmitt trigger bufferto address the problem of inputsignals with slow rise times andlow level noise (approximately<1 V). The cleaned up signalsare then passed to a four-bitdelay filter. The signals on eachchannel are sampled on risingclock edges. A time history of thesignals is stored in the four-bitshift register. Any change on the

input is tested for a stable levelbeing present for three

consecutive rising clock edges.Therefore, the filtered outputwaveforms can change only afteran input level has the same valuefor three consecutive rising clockedges. Refer to Figure 8 whichshows the timing diagram. Theresult of this circuitry is that

short noise spikes between risingclock edges are ignored andpulses shorter than two clockperiods are rejected.

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Figure 7. Simplified Digital Noise Filter Logic.

Quadrature Decoder

The quadrature decoder decodesthe incoming filtered signals intocount information. This circuitrymultiplies the resolution of theinput signals by a factor of four(4X decoding). When using anencoder for motion sensing, theuser benefits from the increasedresolution by being able toprovide better system control.The quadrature decoder samplesthe outputs of the CHA and CHBfilters. Based on the past binarystate of the two signals and thepresent state, it outputs a countsignal and a direction signal to8

the internal position counter. Inthe case of the HCTL-2020, thesignals also go to external pins 5and 16 respectively.

Figure 9 shows the quadraturestates and the valid state transi-tions. Channel A leading channelB results in counting up. ChannelB leading channel A results incounting down. Illegal statetransitions, caused by faulty

encoders or noise severe enoughto pass through the filter, willproduce an erroneous count.

Design Considerations

The designer should be awarethat the operation of the digitalfilter places a timing constrainton the relationship between

incoming quadrature signals andthe external clock. Figure 8shows the timing waveform withan incremental encoder input.Since an input has to be stablefor three rising clock edges, theencoder pulse width (tE - low orhigh) has to be greater than threeclock periods (3tCLK). This

guarantees that the asynchronousinput will be stable during threeconsecutive rising clock edges. Arealistic design also has to take

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into account finite rise times ofchannels. Therefore, tES (encoderthe waveforms, asymmetry of thestate period) > tCLK. Thewaveforms, and noise. In thedesigner must account for

presence of large amounts ofdeviations from the nominal 90noise, tE should be much greaterdegree phasing of input signals tothan 3tCLK to allow for theguarantee that tES > tCLK.interruption of the consecutivelevel sampling by the three-bitPosition Counter

delay filter. It should be notedThis section consists of a 12-bitthat a change on the inputs that(HCTL-2000) or 16-bit (HCTL-is qualified by the filter will2016/2020) binary up/downinternally propagate in a maxi-counter which counts on risingmum of seven clock periods.clock edges as explained in theQuadrature Decoder Section. AllThe quadrature decoder circuitry12 or 16 bits of data are passedimposes a second timing con-to the position data latch. Thestraint between the external clocksystem can use this count data inand the input signals. There mustseveral ways:

be at least one clock period

between consecutive quadratureA. System total range is ≤ 12 or

states. As shown in Figure 9, a16 bits, so the count repre-quadrature state is defined bysents “absolute” position.consecutive edges on both

B. The system is cyclic with ≤12 or 16 bits of count percycle. RST is used to resetthe counter every cycle andthe system uses the data tointerpolate within the cycle.C. System count is > 8, 12, or 16bits, so the count data isused as a relative or incre-mental position input for asystem software computationof absolute position. In thiscase counter rollover occurs.In order to prevent loss ofposition information, theprocessor must read theoutputs of the IC before thecount increments one-half ofthe maximum count capabil-

Figure 9. 4x Quadrature Decoding.

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ity (i.e. 127. 2047, or 32,767quadrature counts). Two’s-complement arithmetic isnormally used to computeposition from these periodicposition updates. Threemodes can be used:

1. The IC can be put in 8-bitmode by tying the SELline high, thus simplify-ing IC interface. Theoutputs must then beread at least once every127 quadrature counts.2. The HCTL-2000 can beused in 12-bit mode andsampled at least onceevery 2047 quadraturecounts.

3. The HCTL-2016 or 2020can be used in 16-bitmode and sampled atleast once every 32,767quadrature counts.

D. The system count is > 16 bitsso the HCTL-2020 can becascaded with other stand-ard counter ICs to giveabsolute position.Position Data Latch

The position data latch is a 12/16-bit latch which captures theposition counter output data oneach rising clock edge, exceptwhen its inputs are disabled bythe inhibit logic section duringtwo-byte read operations. Theoutput data is passed to the businterface section. When active, asignal from the inhibit logicsection prevents new data frombeing captured by the latch,keeping the data stable whilesuccessive reads are madethrough the bus section. Thelatch is automatically reenabledat the end of these reads. Thelatch is cleared to 0 asynchron-ously by the RST signal.

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Inhibit Logic

The Inhibit Logic Section samplesthe OE and SEL signals on thefalling edge of the clock and, inresponse to certain conditions(see Figure 10 below), inhibitsthe position data latch. The RSTsignal asynchronously clears theinhibit logic, enabling the latch. Asimplified logic diagram of theinhibit circuitry is illustrated inFigure 11.

Bus Interface

The bus interface section consistsof a 16 to 8 line multiplexer andan 8-bit, three-state outputbuffer. The multiplexer allowsindependent access to the lowand high bytes of the positiondata latch. The SEL and OEsignals determine which byte is

output and whether or not theoutput bus is in the high-Z state.In the case of the HCTL-2000 thedata latch is only 12 bits wideand the upper four bits of thehigh byte are internally set tozero.

Quadrature Decoder Output(HCTL-2020 Only)

The quadrature decoder outputsection consists of count and up/down outputs derived from the4X decode logic of the HCTL-2020. When the decoder hasdetected a count, a pulse, one-half clock cycle long, will be

output on the CNTDCDR pin. Thisoutput will occur during the clockcycle in which the internal

counter is updated. The U/D pinwill be set to the proper voltage

level one clock cycle before therising edge of the CNTDCDRpulse, and held one clock cycleafter the rising edge of theCNTDCDR pulse. These outputsare not affected by the inhibitlogic. See Figures 5 and 12 fordetailed timing.

Cascade Output (HCTL-2020 Only)The cascade output also consistsof count and up/down outputs.When the HCTL-2020 internalcounter overflows or underflows,a pulse, one-half clock cycle long,will be output on the CNTCAS pin.This output will occur during theclock cycle in which the internalcounter is updated. The U/D pinwill be set to the proper voltagelevel one clock cycle before therising edge of the CNTCAS pulse,and held one clock cycle after therising edge of the CNTCAS pulse.These outputs are not affected bythe inhibit logic. See Figures 5and 12 for detailed timing.

StepSEL123

LHX

OECLKLLH

InhibitSignal

110

Action

Set inhibit; read high byteRead low byte; starts resetCompletes inhibit logic reset

Figure 10. Two Byte Read Sequence.

Figure 11. Simplified Inhibit Logic.

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INTERNAL COUNTER󰀀ROLL OVERCLKFF00CHAFILT*START INHIBITCHBFILT*U/DCNTDCDR*CNTCASCOUNTFFFDHFFFEHFFFFH0000HFFFFHFFFDH*CHAFILT AND CHBFILT ARE THE OUTPUTS󰀀OF THE DIGITAL NOISE FILTER (SEE FIGURES 7 AND 8).Figure 12. Decode and Cascade Output Diagram.

Cascade Considerations(HCTL-2020 Only)

The HCTL-2020’s cascadingsystem allows for position readsof more than two bytes. Thesereads can be accomplished bylatching all of the bytes and thenreading the bytes sequentiallyover the 8-bit bus. It is assumedhere that, externally, a counterfollowed by a latch is used tocount any count that exceeds 16bits. This configuration is

compatible with the HCTL-2020internal counter/latchcombination.

Consider the sequence of eventsfor a read cycle that starts as theHCTL-2020’s internal counterrolls over. On the rising clockedge, count data is updated in theinternal counter, rolling it over. Acount-cascade pulse (CNTCAS)11

will be generated with some delayafter the rising clock edge (tCHD).There will be additional

propagation delays through theexternal counters and registers.Meanwhile, with SEL and OE lowto start the read, the internal

latches are inhibited at the fallingedge and do not update again tillthe inhibit is reset. If the CNTCASpulse now toggles the externalcounter and this count getslatched a major count error willoccur. The count error is becausethe external latches get updatedwhen the internal latch isinhibited.

Valid data can be ensured by

latching the external counter datawhen the high byte read is started(SEL and OE low). This latchedexternal byte corresponds to the

count in the inhibited internallatch. The cascade pulse thatoccurs during the clock cyclewhen the read begins gets

counted by the external counterand is not lost.

For example, suppose the HCTL-2020 count is at FFFFH and anexternal counter is at F0H, withthe count going up. A count

occurring in the HCTL-2020 willcause the counter to roll over anda cascade pulse will be generated.A read starting on this clock cyclewill show FFFFH from the HCTL-2020. The external latch shouldread F0H, but if the host latchesthe count after the cascade signalpropagates through, the externallatch will read F1H.

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General Interfacing

The 12-bit (HCTL-2000) or 16-bit(HCTL-2016/2020) latch andinhibit logic allows access to 12or 16 bits of count with an 8-bitbus. When only 8-bits of countare required, a simple 8-bit (1-byte) mode is available by

holding SEL high continuously.This disables the inhibit logic. OEprovides control of the tri-statebus, and read timing is shown inFigures 2 and 3.

For proper operation of theinhibit logic during a two-byteread, OE and SEL must besynchronous with CLK due tothe falling edge sampling of OEand SEL.

The internal inhibit logic on theHCTL-20XX family inhibits thetransfer of data from the counterto the position data latch duringthe time that the latch outputs arebeing read. The inhibit logic

allows the microprocessor to first

read the high order 4 or 8 bitsfrom the latch and then read thelow order 8 bits from the latch.Meanwhile, the counter cancontinue to keep track of thequadrature states from the CHAand CHB input signals.Figure 11 shows the simplifiedinhibit logic circuit. Theoperation of the circuitry isillustrated in the read timingshown in Figure 13.

*OE can consist of two short low pulses, as well as one long pulse, and still satisfythe inhibit logic sequence. During the time that OE is high, the data lines are tri-seated.Figure 13. Typical Interface Timing.

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Actions

1. On the rising edge of the clock,counter data is transferred tothe position data latch,

provided the inhibit signal islow.

2. When OE goes low, the

outputs of the multiplexer areenabled onto the data lines. IfSEL is low, then the high orderdata bytes are enabled onto thedata lines. If SEL is high, thenthe low order data bytes areenabled onto the data lines.13

3. When the IC detects a low onlow on OE during a fallingOE and SEL during a fallingclock edge.

clock edge, the internal inhibitsignal is activated. This blocks6. When OE goes high, the datanew data from being

lines change to a high imped-transferred from the counter toance state.

the position data latch.

7. The IC detects a logic high onOE during a falling clock edge.4. When SEL goes high, the dataThis satisfies the second resetoutputs change from the highcondition for the inhibit logic.

byte to the low byte.

5. The first of two reset condi-tions for the inhibit logic ismet when the IC detects alogic high on SEL and a logic

Interfacing the HCTL-2020 to a Motorola 6802/8 and Cascading the Counter for 24 Bits

Figure 14. A Circuit to Interface to the 6802/8.

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In this circuit an interface to aused to clock the HCTL-2020.Motorola 6802/8 and a cascadingAddress AO is connected directlyscheme for a 24-bit counter areto the SEL pin on the HCTL-shown. This circuit provides a2020. This line selects the low orminimum part count by: 1) usinghigh byte of data from the HCTL-two 74LS697 Up/Down counters2020.

with output registers and tri-stateoutputs and 2) using a MotorolaCascading is accomplished by6802/8 LDX instruction whichconnecting the CNTCAS output onstores 16 bits of data into the

the HCTL-2020 with the counterindex registers in two consecutiveclock (CCK) input on bothclock cycles.

74LS697s. The U/D pin on theHCTL-2020 and the U/D pin onThe HCTL-2020 OE and theboth 74LS697s are also directly74LS697 G lines are decodedconnected for easy expansion.from Address lines A15-A13. ThisThe RCO of the first 4-bit

results in counter data being74LS697 is connected to the ENTenabled onto the bus wheneverpin of the second 74LS697. Thisan external memory access is

enables the second counter onlymade to locations 4XXX or 2XXX.when there is a RCO signal on theAddress line A12 and processorfirst counter.

clock E enables the 74LS138.The processor clock E is also

This configuration allows the

6802 to read both data bytes with

AddressFunction

CXXXReset Counters

4XXXEnable High Byte on Data Lines2XX0Enable Mid Byte on Data Lines2XX1

Enable Low Byte on Data LinesRead Example

LDX 2000Loads mid byte and then low byte intoSTX 0100memory locations 0100 and 0101LDAA 4000Loads the high byte into memorySTAA 0102location 0102

Figure 15. Memory Addresses and Read Example.

15

a single double-byte fetchinstruction (LDX 2XX0). Thisinstruction is a five cycle

instruction which reads externalmemory location 2XX0 and storesthe high order byte into the highbyte of the index register.Memory location 2XX1 is nextread and stored in the low orderbyte of the index register. Thehigh byte of counter data isclocked into the 74LS697

registers when SEL is low andOE goes low. This upper byte canbe read at any time by pulling the74LS697 G low when readingaddress 4XXX. Figure 15 showsmemory addresses and gives anexample of reading the HCTL-2020. Figure 16 shows theinterface timing for the circuit.

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HCTL-2020󰀀INTERNAL CLOCKFFFF0000CLKSELOEINTERNAL󰀀INHIBITCNTCASRCKGDATA󰀀BUSHIGH ZMID󰀀BYTELOW󰀀BYTEHIGH󰀀BYTEACTIONS11123456710Figure 16. Interface Timing for the 6802/8.

Actions

1. The microprocessor clockoutput is E. If the internalHCTL-2020 inhibit is notactive, new data is trans-ferred from the internalcounter to the position datalatch.

2. An even address output

from the 6802 causes SEL togo low. When E goes high,the address decoder outputfor the HCTL-2020 OE

signal goes low. This causesthe HCTL-2020 to outputthe middle byte of the

system counter (high byte ofthe HCTL-2020 counter).This middle byte, FFFFH isavailable at (2) through (4),the first time OE is low. Inthis example an overflow16

has occurred and OE hasbeen pulled low to start aread cycle. SEL and OE aregated to give RCK whichlatches the external highbyte, equal to 00H. Thefalling edge, of the CNTCASsignal counts up the

external counter to 0001H.3. With the first negative edgeof the clock after SEL andOE are low the internallatches are inhibited fromcounting and the 6802 readsthe high byte in.

4. OE goes high and the databus goes into a highimpedance state.

5. OE is low and SEL is highand the low byte is enabledonto the data bus. The lowbyte is valid through (7).

6. With the first negative edgeafter OE and SEL go high,the first of the two HCTL-2020 inhibit reset conditionsis met and the 6802 readsthe low byte in.

7. The data bus returns to thehigh impedance state, whenOE goes high.

8. With the first negative edgeof the clock after OE goeshigh, inhibit reset iscomplete.

9. With the positive going edgeof the clock, G is assertedand the external high byte,00H is available on the databus from 9 through 10 andthe 6802 reads the high bytein at (10).

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Interfacing the HCTL-20XX to anIntel 8748

The circuit shown in Figure 17shows the connections betweenan HCTL-20XX and an 8748.Data lines D0-D7 are connectedto the 8748 bus port. Bits 0 and 1of port 1 are used to control theOE and SEL inputs of the HCTL-20XX respectively. T0 is used toprovide a clock signal to the

HCTL-20XX. The frequency of T0

is the crystal frequency dividedby 3. T0 must be enabled byexecuting the ENT0 CLKinstruction after each systemreset, but prior to the firstencoder position change. An8748 program which interfacesto the circuit in Figure 17 is

given in Figure 18. The resultinginterface timing is shown inFigure 19.

LOC00000200300400600800900B

ObjectCode99 0008 A8 0208 A9 03

SourceStatementsANL P1, 00HINS A, BUSMOVE R0, AORL P1, 02HINS A, BUSMOV R1, A ORL P1, 03H

Comments

Enable output and higher orderbits

Load higher order bits into ACCMove data to register 0Enable output and lower orderbits

Load order bits into ACMove data to register 1Disable outputsReturn

93 RETR Figure 18. A Typical Program for Reading HCTL-20XX with an 8748.

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ANL P1, OOH

ORL P1, 02H

Figure 19. 8748 READ Cycle from Figure 18.

Actions

1. ANL P1, 00H has just beenexecuted. The output of bits 0and 1 of Port 1 cause SEL andOE to be logic low. The datalines output the higher orderbyte.

2. The HCTL-20XX detects thatOE and SEL are low on thenext falling edge of the CLKand asserts the internal inhibitsignal. Data can be read

without regard for the phase ofthe CLK.

3. INS A, BUS has just been

executed. Data is read into the8748.

4. ORL PORT 1, 02H has justbeen executed. The programsets SEL high and leaves OElow by writing the correctvalues to port 1. The HCTL-

20XX detects OE is low andSEL is high on the next fallingedge of the CLK, and thus thefirst inhibit reset condition ismet.

5. INS A, BUS has just beenexecuted. Lower order databits are read into the 8748.6. ORL P1, 03H has just beenexecuted. The HCTL-20XXdetects OE high on the nextfalling edge of CLK. The

program sets OE and SEL highby writing the correct values toport 1. This causes the datalines to be tristated. This

satisfies the second inhibit andreset condition. On the nextrising CLK edge new data istransferred from the counter tothe position data latch.

Additional Information from AvagoTechnologies

Application briefs are availablefrom the factory. Please contactyour local Avago sales

representative for the following.M027 Interfacing the HCTL-20XX

to the 8051

M019 Commonly Asked

Questions about the HCTL-2020 and Answers

M020 A Simple Interface for the

HCTL-2020 with a 16-bitDAC without Using aProcessor

M023 Interfacing the MC68HCII

to the HCTL-2020

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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5965-E5988-55EN June 2, 2006