Logic translation method for increasing simulation

专利名称：Logic translation method for increasing

simulation emulation efficiency

发明人：Wilm Ernst Donath,Helmut Roth申请号：US08/662383申请日：19960613公开号：US05761488A公开日：19980602

摘要：A method of speeding up computer simulation/emulation of circuit logicdesigns. The method converts an original circuit logic design (intended for hardwarepackaging) to a different circuit form before starting computer simulation/emulation. Theconverted circuit form provides the same simulation/emulation results as would havebeen obtained with the original logic circuit. The method operates with multi- phase logicdesigns comprised of gate circuits using multi-phase clocking of the type commonlypackaged in semiconductor chips. The method converts such multi- phase logic designsinto a single-phase circuit form, which is presented to the computer for

simulation/emulation that provides the same results as the multi-phase logic design butat a much faster speed. The method is presented with a multi-phase logic designcontaining flip- flops as the internal storage circuits. The method effectively retains thestorage circuits found in a multi-phase logic design and replicates its logic blocksproviding multiple phase outputs. Then the storage circuits are reconnected to theoriginal and replicated logic blocks in a manner that enables a single clock cycle tooperate the converted logic design to simulate/emulate the same results in the storagecircuits, as if the original multi-phase logic design were being simulated or emulated, but

at a much faster speed.

申请人：INTERNATIONAL BUSINESS MACHINES CORPORATION

代理人：Bernard M. Goldman

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