APL10312-7_Programming_the_200_and_300_Series Z-Wave Single Chip Flash

Application Note

Programming the 200 and 300 Series Z-Wave Single Chip Flash

Document No.:

APL10312

Version: 7

This note describes the operations necessary in order to program the Flash, Lock Bits, and Infodata in the 200 Series and 300 Series Z-Wave Single Chips via the SPI interface MVO;TJC;TJO

Description:

Written By:

Date: 2007-03-02 Reviewed By:

JMI;OPP;SSE

Restrictions: None

Approved by:

Date CET Initials Name Justification 2007-03-02 08:52:32 NTJ Niels Thybo Johansen

This document is the property of Zensys A/S. The data contained herein, in whole or in part, may not be duplicated, used or disclosed outside the recipient for any purpose other than to conduct technical

evaluation. This restriction does not limit the recipient's right to use information contained in the data if it is obtained from another source without restriction.

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APL10312-7

Programming the 200 and 300 Series Z-Wave Single Chip Flash 2007-03-02

REVISION RECORD

Doc. Part Date By Section No affected 903900900 20040115 MVO ALL 903900901 20041102 MVO 3.3.3

3.3.4 3.3.9 3.3.10 4

Brief description of changes

Initial version

Set write cycle time changed for ‘Chip Erase’ and ‘Program Memory Erase’ Set write cycle time changed for ‘Chip Erase’ Example elaborated

Duration of ‘Write Lock Bits’ changed and example elaborated

Set write time changed for ‘Chip Erase’, ‘Program Memory Erase’, ‘Write Lock Bits’ and ‘Write Infodata’. The minimum time RESET_N must asserted before programming mode is enabled changed.

903900902 20041111 MVO 3.3.3 Set write cycle time changed for ‘Chip Erase’ and ‘Program Memory Erase’ to the

same as for other commands 3.3.4 Set write cycle time changed for ‘Chip Erase’ to the same as for other commands 3.3.9 Added constraint on tWP 4 Changed tpower-up and tExt_clk time

903900903 20050407 MVO 5.1 Section added

5.4 Section added 6 Reference to ZW0201 Datasheet for Developer’s Kit v4.00 instead of Short Form

datasheet

903900904 20050628 MVO 5.2 Changed VSS to VPP at pin 8

All Changed HomeID to Infodata

st

6 20050118 MVO All New 1 page/header/footer contents. New Doc No 7 20070129 MVO All Included the 300 series chip

3.3.3 New tWC upper limit

Clarified the explanations of the “wait delays” 3.3.4,

3.3.5,

3.3.6, 3.3.8, 3.3.10, 3.3.13

20070301 MVO 3.3.5 Added info about how delays can be calculated

3.3.6 5.2 Removed the info saying that the VPP is reserved for future use All Added missing doc reference

Added missing ref to the 300 series

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Table of Contents

1 2 2.1 2.2 3

ABBREVIATIONS.................................................................................................................................1 INTRODUCTION...................................................................................................................................1 Purpose..............................................................................................................................................1 Audience and prerequisites................................................................................................................1 PROGRAMMING THE FLASH.............................................................................................................2

3.1 Flash Memory.....................................................................................................................................2 3.1.1 Lock Bits...................................................................................................................................2 3.1.2 Infodata....................................................................................................................................3 3.2 SPI Programming Hardware interface...............................................................................................3 3.2.1 SPI and Control signals............................................................................................................3 3.2.2 System Clock...........................................................................................................................4 3.3 SPI Protocol and Instructions.............................................................................................................5 3.3.1 Read Operations......................................................................................................................6 3.3.2 Programming Enable...............................................................................................................7 3.3.3 Set Write Cycle Time...............................................................................................................8 3.3.4 Chip Erase...............................................................................................................................9 3.3.5 Program Memory Erase...........................................................................................................9 3.3.6 Page Erase..............................................................................................................................9 3.3.7 Read Program Memory..........................................................................................................10 3.3.8 Load Program Memory Page.................................................................................................10 3.3.9 Write Program Memory Page.................................................................................................10 3.3.10 Write Lock Bits.......................................................................................................................11 3.3.11 Read Lock Bits.......................................................................................................................12 3.3.12 Read Signature Byte..............................................................................................................13 3.3.13 Write Infodata.........................................................................................................................13 3.4 Programming Sequence...................................................................................................................13 4 5 5.1 5.2 5.3 5.4 6

PROGRAMMING TIMING...................................................................................................................15 SPECIFICATIONS FOR PROGRAMMING........................................................................................17 XOSC signal specification................................................................................................................17 Pin Configuration..............................................................................................................................18 Package Type and Outlines.............................................................................................................19 Device Marking.................................................................................................................................20 REFERENCES....................................................................................................................................21

Flash Memory...................................................................................................................22 SPI Programming Hardware Interface..............................................................................22 Protocol and Instructions..................................................................................................22 Programming Sequence...................................................................................................22 Programming Timing........................................................................................................22

APPENDIX A UPGRADING A ZW0102 PROGRAMMING DEVICE.....................................................22 Appendix A.1 Appendix A.2 Appendix A.3 Appendix A.4 Appendix A.5

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1 ABBREVIATIONS

Abbreviation Explanation BOBLOCK BOot Block LOCK BSIZE Boot Sector Size CPU Central Processing Unit Infodata 4 bytes static data stored in information page in the flash IC Integrated Circuit MISO Master In Slave Out MOSI Master Out Slave In MSB Most Significant Bit MSL Least Significant Bit SCK Serial ClocK SPI Serial Peripheral Interface SPIRE SPI read Enable TBD To Be Defined

QFN Quad Flat Non-lead XOSC System clock ZW0102 Zensys 100-Series Z-Wave Single Chip

2 INTRODUCTION

2.1 Purpose

The purpose of this document is to enable readers to build a 200 and/or a 300 Series Z-Wave Single Chip flash programmer. The document describes the protocol and circuit needed for programming the flash, lock bits, and Infodata in the 200 or the 300 Series Z-Wave Single Chips. Refer to [1] and to [2] for a more detailed description of the 200 Series Z-Wave Single Chip and the 300 Series Z-Wave Single Chip respectively.

Section 3 in this document describes the flash, the lock bits, the Infodata, the programming circuit, and the programming protocol and instructions. Section 5 contains the physical specification of the 200 and the 300 Series Z-Wave Single Chips. 2.2

Audience and prerequisites

This document is targeted engineers that are well acquainted with SPI and with IC programming in general.

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3 PROGRAMMING THE FLASH

The internal flash core in the 200 and the 300 Series Z-Wave Single Chip contains a memory block and an information block. The information block is used to store Flash Lock Bits and Infodata.

The flash memory, lock bits, and Infodata are programmed through the SPI interface of the 200 and the 300 Series Z-Wave Single Chips. 3.1 Flash Memory

A 32k bytes embedded flash memory block is integrated in the 200 and the 300 Series Z-Wave Single Chips. This block flash is used as the program memory for an internal CPU core. An additional

information block is used to store lock bits and an Infodata field consisting of 4 bytes can be used to store static data, e.g. calibration data. The flash blocks are programmed from an external SPI interface. Data must be written in blocks of 256 bytes, i.e. the Flash main memory block is divided into 128 pages of 256 bytes each. Each page is page-wise writeable.

The flash can be protected from unintentional write operations from the CPU core and from read back operations from the external SPI interface.

Flash CoreProgram MemoryBlockPage 127Page 12632k bytes256 bytes256 bytes

InformationblockLock bits andInfodataPage 1Page 0256 bytes256 bytes

Figure 1. Flash Core components

3.1.1 Lock Bits

The function of the Lock Bits is to:

•

• •

enable read-back protection of the (entire) flash,

enable protection of page 0 against inadvertent writing,

enable and set the size of a boot sector that is a part of the flash which is secured against inadvertent writing.

The Lock Bits are stored in the information page of the flash core and can only be read from the SPI interface.

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3.1.2 Infodata

4 bytes can be stored in an information block in the flash core. The Infodata can only be programmed from the external SPI interface, whereas it can be read from both the external SPI interface and from the internal CPU. 3.2

SPI Programming Hardware interface

This section describes the hardware interface needed for programming the flash memory, lock bits, and Infodata.

The following figure depicts the circuit needed for programming the embedded flash.

VDD27AVDD_RF26AVDD_SY31AVDD_IF30RX_IND28TX_IND29RF_IO32VSS25VSSVDDN.C.1N.C.2RESET_N3P1.7/INT14P1.6/PWM/INT05P1.56P1.4/SCK7N.C.8P1.2/MISO10DVDD_IO11DVDD12N.C.13DVDD14N.C.15P1.3/MOSIDVDD16924AVDD_COExposed pad23XOSC_Q122XOSC_Q2To clocksourceVSS21VSS20P0.0/ADC0/ZEROX19P0.1/ADC1/TRIAC18P1.0/ADC2/TXD17P1.1/ADC3/RXDVDDTo programmingunitFigure 2 Overview of required circuitry for programming the 200 or the 300 Series Z-Wave single chip

(Refer to Figure 4 and Figure 5 regarding the clock source)

The device must be powered during programming, i.e. all power pins (*VDD*) and ground pins (VSS) must be connected to the power supply, see section 5.2.

An external clock or a crystal must be present during flash programming, see section 3.2.2. 3.2.1

SPI and Control signals

The SPI interface consists of two data signals (MOSI and MISO) and a clock signal (SCK). The only control signal of the reset signal (RESET_N). Refer to [1] for further description of the SPI interface. The programming interface is active when RESET_N has been asserted low for more than 217clock cycles (~4.1ms @ crystal frequency=32 MHz). The programming timing is shown in

Figure 13 and Figure 14. The SPI interconnection and control pins are shown in Figure 3.

During flash programming an external SPI master must take over the control of the SPI bus. The 200 and the 300 Series Z-Wave Single Chips’ SPI interface will automatically be set up as SPI slave when

programming mode is enabled. All other programmable ports will be tri-stated. Figure 3 gives a simplified block diagram of a typical interface to programming equipment.

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RESET_NRESET_NPROGRAMMING UNITSCKMOSIMISO200/300 Series Z-WaveP1.4/SCKP1.3/MOSISingle ChipP1.2/MISOFigure 3. Interface to Programming Equipment

3.2.2 System Clock

The 200 or the 300 Series Z-Wave Single Chip must have a system clock (XOSC) running during programming. This system clock can either be applied as an external clock signal (see Figure 5) or by the means of an external crystal. If the crystal solution is used the following components must be connected (as depicted in Figure 4):

A. A crystal Q1 (16 or 32MHz)

B. Two load capacitors C1 and C2

The value of the capacitors depend on the crystal type, refer to the datasheet of the crystal.

200/300 SeriesZ-Wave Single ChipXOSC_Q2X1C1XOSC_Q1C2Figure 4. Components needed for programming when using a crystal

The external clock signal must be in the range 16-MHz and must a be square wave. Refer to section 5.1 for details on the electrical characteristics of the XOSC signal. Furthermore the external clock signal must be connected to XOSC_Q1 as depicted in Figure 3.

200/300 SeriesZ-Wave Single ChipXOSC_Q2XOSC_Q1N.C.EXTERNALCLOCK

Figure 5. Components needed for programming when using external clock source

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3.3 SPI Protocol and Instructions

In flash programming mode the SPI clock SCK is low in the idle state, the SPI data (MISO and MOSI) is read on the rising edge of SCK and clocked out on the falling edge of SCK, as depicted in Figure 6.

SCK

MOSI / MISO

763210

Figure 6: SPI protocol in flash programming mode

Table 1 shows the programming instruction format. The serial protocol addresses on 16 bit boundaries. The H bit select odd or even byte during read or write operations (odd byte when H=1). Erase can be done on the entire device, on the program memory only, or a single flash page. A memory space must be erased before programming it. Flash locations contain FFh when erased. The serial programming instruction set is described below: Ledged:

a: Page address

b: Even byte address

H: Odd or even (high or low) byte c: Clock timing bits

s: Signature byte address i: Input data o: Output data

w: Infodata word (most/least significant) x: Don’t care

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Table 1, Serial programming instruction set

Instruction

(click to jump to description)

Instruction Format Byte 1 Byte 2 Byte 3

101011001010110001010011100xxxxxxxxxxxxxxxxxxxxxOperation

Byte 4

xxxxxxxxEnable serial programming after reset

has been low tPE, see section 4.

xxxxxxxxChip erase. Clears all pages, including

the information block containing lock bits and Infodata.

xxxxxxxxProgram Memory Erase. Clears all

pages, excluding the Infodata and the lock-bits.

xxxxxxxxErase Program Memory page at

address a.

ooooooooRead H (high or low) data o at flash

Program Memory address a:b:H

iiiiiiiiWrite data i to SRAM page buffer at

address b:H

xxxxxxxxWrite the loaded SRAM page buffer to

flash Program Memory address a.

xxx43210Read lock bits. ‘1’ = unprogrammed. ‘0’

= programmed

00043210Write Lock Bits. Set bits 4-0 to ‘0’ to set

lock on flash.

xxccccccSet number of clock cycles for flash

programming time.

ooooooooRead signature byte o at address s iiiiiiiiWrite the Infodata of the ASIC in flash.

w is the 16 bit address, i is 16 bits of the Infodata. At w = 0, Byte 3 equals the most significant byte of the

Infodata. At w = 1, Byte 4 equals the least significant byte of the Infodata.

ooooooooRead the Infodata of the ASIC from

flash. w is the 16 bit address, o is 16 bits of the Infodata. At w = 0, Byte 3 equals the most significant byte of the Infodata. At w = 1, Byte 4 equals the least significant byte of the Infodata.

Programming enable Chip Erase

Program Memory Erase Page Erase

Read Program Memory

10101100101xxxxxxxxxxxxx101011000010H000110xxxxxxaaaaaaaxxxxxxxxxaaaaaaaxxxxxxxx111xxxxx01011101xxxxxxxx000wxxxxxaaaaaaabbbbbbbxbbbbbbbxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxsssiiiiiiiiLoad Program Memory Page 0100H000Write Program Memory Page 01001100Read Lock Bits Write Lock Bits Set Write Cycle Time Read Signature Byte

Write Infodata

0101100010101100101011000011000010101100Read Infodata

10101100001wxxxxoooooooo

Each instruction is sent in the order bytes 1 to 4, most significant bits first (MSB). MSB is leftmost in all bit fields in the table. All 4 bytes must be sent, even if the last bits are ‘x’ - don’t care. 3.3.1 Read Operations

When a read operation is performed (‘Read Program Memory’, ‘Read Lock Bits’, ‘Read Infodata’, or ‘Read Signature Byte’) it will take up to 36 system clock cycles before valid read data are available on the SPI data output. That is, the programming unit (SPI master) must wait 36 system clock cycles before sending the first positive edge on SCK after sending the last negative edge of SCK for byte 3 as depicted in Figure 7.

Byte 1Byte 2Byte 3Byte 436 system clockperiodsSCKMOSIMISOFigure 7. Read instruction timing (Refer to Figure 8 for timing of the ‘Read Infodata’ instruction)

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Note that for the ‘Read Infodata’ instruction the programming unit (SPI master) must wait 36 system clock cycles before sending the first positive edge on SCK after sending the last negative edge of SCK for byte 2 as depicted in Figure 8.

Byte 1Byte 2Byte 3Byte 436 system clockperiodsSCKMOSIMISOFigure 8. Read Infodata’ instruction timing (Refer to Figure 7 for timing of other read instructions)

3.3.2 Programming Enable

The ‘Programming Enable’ instruction is used to enable the flash interface for communication and to do byte-synchronization. A flowchart for SPI communication is given in Figure 9. The 200 or the 300 Series Z-Wave Single Chip must be powered-on and it must have a stable system clock running, i.e. wait for tpower-up after power is applied. See section 3.4 for a full programming sequence description.

Figure 9 show the procedure for enabling programming mode and to synchronize. The synchronization has taken place when the 200 or the 300 Series Z-Wave single chip echoes the second byte of the programming enable instruction back while reading byte 3.

The synchronization normally takes 1-2 attempts, but may take up to 32 attempts.

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Set RESET_N lowWait tEPWrite 'Programming Enable' byte 1Write 'Programming Enable' byte 2Read 'Programming Enable' byte 3Read 'Programming Enable' byte 4Chip Synchronised?(if synchronised second byte ofinstruction was echoed back whenissuing clocks for the third byte)NoApply positive pulse on SCKYesSend 1. InstructionSend n. InstructionFigure 9. Enabling Flash Interface

3.3.3 Set Write Cycle Time

Before writing to the flash the write cycle time, tWC, must be set in accordance with the device clock oscillator period (TXOSC):

20μs ≤ tWC ≤ 30μs

The lowest legal value of tWC (20μs) gives the fastest programming time.

tWC = c . . TXOSC , where c is the value set by the ‘Set Write Cycle Time’ instruction 20μs ≤ tWC ≤ 30μs ⇒ ⎡20μs/( . TXOSC)⎤ ≤ c ≤ ⎣30μs/( . TXOSC)⎦

Use the lowest possible value of c that fulfills the equation above. Example – find the lowest (fastest) value of c :

TXOSC = (16MHz)-1 ⇒ c = ⎡20μs. 16MHz /⎤ = 5 = 000101b

Table 2, Suggested values for Set Write Cycle

X-Tal Frequency

16 MHz 32 MHz MHz

Int. system clock

4 MHz 8 MHz 16 MHz c min (≥20 μs) c max (≤30 μs)

000101 000111 001010 001110 010100 011100

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3.3.4 Chip Erase

Executing the ‘Chip Erase’ instruction restores the contents of all memory locations to FF (hex) on the entire flash, i.e program memory, lock bits, and Infodata.

The programming unit has to wait at least 200ms for the minimum value of tWC and at least 300ms for the maximum value of tWC, after writing the ‘Chip Erase’ instruction (see section 3.3.3).and before a new instruction can be issued.

The erase operation processing time, tER, can be calculated from

tER = tWC . 10000

Example - Using a clock or crystal frequency of 16MHz and using the fastest programming speed setting (tWC = 20μs):

c = ⎡20μs /( . (16MHz)-1)⎤ = 5 (c is the value set by the ‘Set Write Cycle Time’ instruction) ⇒ tWC = c . . TXOSC = 5 . . (16MHz)-1 = 20μs ⇒ tER = tWC . 10000 = 20μs . 10000 = 200ms

3.3.5

Program Memory Erase

Executing the ‘Program Memory Erase’ instruction restores the contents of all locations in the Program Memory block (32k bytes) to FF (hex). The ‘Chip Erase’ instruction must be used to clear the locks bit and the Infodata.

The Infodata and Lock Bits will not be erased by a ‘Program Memory Erase’ instruction.

Like for the ‘Chip Erase’ instruction the programming unit has to wait, after writing the ‘Program Memory Erase’ instruction, depending on the ’Write Cycle Timing’ setting, see sections 3.3.3 and 3.3.4. The erase operation processing time, tER, can be calculated from

tER = tWC . 10000

3.3.6 Page Erase

The ‘Page Erase’ instruction can be used to restore one program memory page to FF (hex). The programming unit has to wait between 20ms to 30ms, after writing the ‘Page Erase’ instruction, depending on the ’Write Cycle Timing’ setting, see sections 3.3.4. The erase operation processing time, tEP, can be calculated from

tEP = tWC . 1000

The Infodata and Lock Bits will not be erased by a ‘Page Erase’ instruction.

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3.3.7 Read Program Memory

Reads a byte at a given address in flash. Please refer to section 3.3.1 regarding the timing of the processing of the instruction. 3.3.8

Load Program Memory Page

Writing to a program memory flash page is performed in the following manner:

1. Write each byte that should be updated to a buffer (256 bytes located in SRAM) using the

instruction ‘Load Program Memory Page’.

2. Transfer the buffer to the flash using the instruction ‘Write Program Memory Page’.

The programming sequence for one flash page is depicted in Figure 10.

Load byte using 'Load Program Memory Page Instruction' into bufferAll bytes written?NoYesTransfer buffer to Flash memory by issuing 'Write Program Memory Page'Wait at least tWP

Figure 10. Programming One Page

Please note that it is the whole 256 bytes buffer that is transferred from the SRAM. The bytes that have not been written by ‘Load Program Memory Page’ may assume random values from the SRAM. 3.3.9

Write Program Memory Page

The ‘Write Program Memory Page’ instruction transfers the content of a 256-byte buffer in SRAM to a page in flash (refer to the description of the ‘Load Program Memory Page’). The programming unit has to wait at least 5.2ms for the minimum tWC value and at least 7.8ms for the maximum tWC value, after writing the ‘Write Program Memory Page’ instruction (See section 3.3.3.) and before it can issue a new instruction.

The ‘Write Program Memory Page’ operation processing time, tWP, can be calculated from

tWP = tWC . 260

Example - using a clock or crystal frequency of 16MHz and using the fastest programming speed setting (tWC = 20μs):

c = ⎡20μs /( . (16MHz)-1)⎤ = 5 (c is the value set by the ‘Set Write Cycle Time’ instruction) ⇒ tWC = c . . TXOSC = 5 . . (16MHz)-1 = 20μs ⇒ tWP = tWC . 260 = 20μs . 260 = 5.2ms

That means that the programming unit has to wait 5.2ms after issuing the ‘Write Program Memory Page’ instruction.

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3.3.10 Write Lock Bits

The function of the ‘Write Lock Bits’ instruction is threefold:

1) To enable read-back protection of the (entire) flash by clearing a dedicated bit, SPIRE (SPI Read

Enable). 2) To enable protection of page 0 against inadvertent writing by clearing a dedicated bit, BOBLOCK

(Boot Block Lock). 3) To define a boot sector that is secured against inadvertent writing. The size of the boot sector is

programmable using 3 dedicated bits, BSIZE (Boot Sector Size). The boot block is from 7FFF(hex) and downwards. Figure 11 depicts an overview of the flash protection.

7FFF (hex)PAGE 127PAGE 126PAGE 125SPIRE -Protects entireflash againstread back(WRITE PROTECTED)BOOT SECTORBSIZE - Determines thesize of the boot sector0000 (hex)PAGE 0BOOT PAGE(The CPU starts excutionin this page after reset)BOBLOCK - Selectswrite protection ofpage 0Figure 11. Overview of Flash Protection

It is not possible to write to the Boot Sector from neither the internal CPU or through the external SPI interface. The boot sector size is programmable in eight steps, from 0 to 32768 bytes through BSIZE, i.e. setting it to 0 bytes disables the protection. When the boot sector is set to 32768 bytes all available flash program memory is write-protected from accesses from both the internal CPU and the external SPI interface.

Table 3 depicts the coding of the individual flash memory lock bits.

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Bit Name Function 7:5 - Reserved, write as ‘0’ 4 BOBLOCK Boot Block Lock

0: Page 0 is write protected

1: Page 0 is writeable, unless BSIZE = 000

3:1 BSIZE Boot Sector Size

000: 32768 bytes (all) 001: 16384 bytes 010: 8192 bytes 011: 4096 bytes 100: 2048 bytes 101: 1024 bytes 110: 512 bytes 111: 0 bytes

0 SPIRE SPI Read Flash Enable

0: SPI interface is not allowed to read flash data 1: SPI interface is allowed to read flash data

Table 3. Flash Memory Lock Bits

All locks are deactivated (set them to 1) when the flash is erased using the ‘Chip Erase’ instruction. If multiple ‘Write Lock Bits’ instructions are issued without chip erase between, each lock bit will be AND’ed together with the previously written lock bit. In effect, this means that it is not possible to unlock the flash memory without also erasing it.

If you have to deactivate the Lock Bits (set them to 1) and the Infodata already has been programmed to the flash, you must first read the Infodata from the flash, do ‘Chip Erase’ (setting the Lock Bits and Infodata bits to 1), and then rewrite the read Infodata to the flash.

The lock bits can only be read through the SPI and not from the internal CPU.

The programming unit has to wait at least 41μs for the minimum tWC value and at least 61.5μs for the maximum tWC value, after writing the ‘Write Lock Bits’ instruction (See section 3.3.3.) and before it can issue a new instruction.

The ‘Write Lock Bits’ operation processing time, tWL, can be calculated from:

tWL = tWC . 2.05

Example - using a clock or crystal frequency of 16MHz and using the fastest programming speed setting (tWC = 20μs):

c = ⎡20μs /( . (16MHz)-1)⎤ = 5 (c is the value set by the ‘Set Write Cycle Time’ instruction) ⇒ tWC = c . . TXOSC = 5 . . (16MHz)-1 = 20μs ⇒ tWL = tWC . 2.05 = 20μs . 2.05 = 41μs

3.3.11 Read Lock Bits

Executing the ‘Read Lock Bits’ instruction reads the status of the lock bits. Please refer to ‘Write Lock Bits’ for a further description and to section 3.3.1 regarding the timing of the processing of the instruction.

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3.3.12 Read Signature Byte

The ‘Read Signature Byte’ instruction reads a signature byte from the chip. For the 200 and 300 Series Z-Wave Single Chip there is 7 signature bytes. The sequence is shown in Table 4.

Signature byte address Value (hex) Meaning

000 7Fh Manufacturer JEDEC ID. 001 7Fh 010 7Fh 011 7Fh 100 1Fh 101 00h Chip Type 110 00h-05h ZW0201 revisions

06h-07h ZW0301 revisions

Table 4. Signature Bytes Please refer to section 3.3.1 regarding the timing of the processing of the instruction. 3.3.13 Write Infodata

The ‘Write Infodata’ instruction is used to set the Infodata that can be stored in the information page of

the flash. The 4 byte Infodata is set 2 bytes at a time.

All Infodata bits are restored (set to 1) when the flash is erased using the ‘Chip Erase’ instruction. If multiple ‘Write Infodata’ instructions are issued without chip erase between, each Infodata bit will be AND’ed together with the previously written Infodata bit.

The Infodata bits can only be programmed through the SPI and not from the internal CPU, but they can be read from both the internal CPU and through the external SPI interface.

The programming unit has to wait at least 61.5μs for the minimum tWC value and at least 81.5μs for the maximum tWC value, after writing the ‘Write Infodata’ instruction (See section 3.3.3 and 3.3.10) and before it can issue a new instruction.

The ‘Read Infodata’ instruction is used to read the Infodata that can be stored in the information page of the flash. The 4 byte Infodata is read 2 bytes at a time. Please refer to section 3.3.1 regarding the timing of the processing of the instruction. 3.4 Programming Sequence

Figure 12 depicts the fastest programming sequence possible.

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StartWrite flash data to SRAM page bufferSet RESET_N and SCK low, apply clocka, and apply powerWrite 2 least significant Infodata bytes to flashWrite SRAM page buffer to flash Program Memory page n++Wait at least tWHWait tPEWait at least tWPEnable programmingNoVerify Infodata ?NoRead SignatureVerify data ?YesRead flash page nYesRead 2 least significant Infodata bytes from flashSet Write Cycle TimingVerificartion succeeded ?YesNoNoDataWriteErrorVerificartion succeeded ?YesNoInfodataWriteErrorErase ChipSet Lock Bits ?YesWrite Lock Bits to flashNoCheck that chip is erased ?YesNoAll data written to flash ?Yesn:=0Write Infodata ?YesNoWait at least tWLRead flash page n++Write 2 most significant Infodata bytes to flashNoEraseErrorVerify Lock Bits ?YesNoAll bytes equals FFh ?YesWait at least tWHn==127 ?YesVerify Infodata ?YesNoRead Lock BitsVerificartion succeeded ?NoSetLock BitsErrorn:=0Read 2 most significant Infodata bytes from flashVerificartion succeeded ?YesNoInfodataWriteErrorDoneFigure 12 Flow chart for a full programming sequence

(Note a: Only apply clock signal if X-Tal isn't mounted)

The programming sequence depicted in Figure 12 is an example of how the programmer devices

algorithm could look. The specific algorithm used in a programming device might look differently as long as the timing is fulfilling the requirements described in this document. A programming algorithm could also include a couple of retries if a certain operation fails.

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APL10312-7 Programming the 200 and 300 Series Z-Wave Single Chip Flash 2007-03-02

4 PROGRAMMING TIMING

Start programmingEnd programming and run deviceVDDXOSCRESET_NSCKMOSIMISOtPower-uptPEtIdletReset,pulseFigure 13. SPI Flash Programming Control Signal Timing

tLowtHightRise90%tFall90%SCK10%10%tDataMISOMOSISlave DataMaster DataSlave DataMaster DatatSetuptHoldFigure 14. SPI Flash Programming Data and Clock Timing

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Parameter

SPI FLASH PROGRAMMING fSCK SCK frequency tLow SCK low period tHigh SCK high period tRise SCK rise time tFall tIdle tSetup tHold tData tPE

SCK fall time

Cond.

Idle before Start Data setup time Data hold time

Delay from SCK falling edge to valid data The minimum time RESET_N must asserted before programming mode is enabled

1tReset,pulse The minimum reset (RESET_N) pulse Tclk - - OPERATION DURATIONS4

tER Flash erase duration 200 - 300 ms tEP Flash page erase duration 20 - 30 ms

1 & 2tACC Read operation access time - 36⋅Tclk tWP Write page duration 5.2 - 7.8 ms tWL Write lock bits duration 41 - 61.5 μs tWH Write Infodata duration 61.5 - 81.5 μs

POWER-UP TIMING

Transition from state To state

Power VDD=3.3V, Stable main crystal - - 100μs + tPower-up

main crystal not oscillation and stable 5120⋅Tclkoscillating. internal mains clock. RESET_n=0. Power VDD=3.3V, Stable internal mains - - 100μs + tExt_clk

external clock signal clock. 5120⋅Tclkis applied to XOSC_Q1-pin.3

Figure 15. SPI timing parameters

Typ Max Unit

1 - - fclk / 32

1- - 16⋅Tclk

1- - 16⋅Tclk

10% to - - Tclk 90% 90% to - - Tclk 10%

Tclk 1 - - Tclk 1 - - Tclk 1 - - - - Tclk 171- - 2⋅Tclk

Min

fclk is the frequency of the system clock (XOSC), that is the X-tal frequency or the frequency of the clock signal applied to the

XOSC_Q1 pin. Tclk is the period of the system clock (= 1/ fclk).

When a read operation is performed it will take up to 36 clock cycles before valid data are available on the SPI data output. The master must wait at least so many clock cycles before sending the first positive edge on SCK after the last negative edge of SCK for byte 3.

321

An external clock signal should only be applied during production or testing and never during normal operation. Use the min value for tWC=20μs and the max value for tWC=30μs

4

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APL10312-7 Programming the 200 and 300 Series Z-Wave Single Chip Flash 2007-03-02

5 SPECIFICATIONS FOR PROGRAMMING

Refer to [1] for at full description of the electrical and mechanical specification of the 200 Series Z-Wave Single Chip.

Refer to [2] for at full description of the electrical and mechanical specification of the 300 Series Z-Wave Single Chip. 5.1

XOSC signal specification

DC Characteristics (VDD =2.1V to 3.6V, unless otherwise specified)

Parameter

XOSC_Q1

Condition

TA= -35 ° to 120 ° TA= -35 ° to 120 °

Min

Typ

Max

Unit

VIH High-level Input Voltage VIL Low-level Input Voltage

0.8 -0.2 1.0 0.0 1.2 0.2 V V

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5.2 Pin Configuration

27AVDD_RF26AVDD_SY31AVDD_IF30RX_IND28TX_IND29RF_IO32(VSS)N.C.1N.C.2RESET_N3P1.7 / INT14P1.6 / PWM / INT05P1.56P1.4 / SCK7(VPP)8P1.2 / MISO10DVDD_IO11DVDD12MAIN13DVDD14SUPP15P1.3 / MOSI9DVDD1625(VSS)24AVDD_CO23XOSC_Q122XOSC_Q221(VSS)20P0.0 / ADC0 / ZEROX19P0.1 / ADC1 / TRIAC18P1.0 / ADC2 / TXD17P1.1 / ADC3 / RXDTop View(VSS on Exposed Pad)

Pin Pin Name Pin Type Pin Pin Name Pin Type

1)E.P. VSS Power 18 P1.0/ADC2/TXD Digital tristate I/O /

2)

analogue input 1 N.C. - 2)

19 P0.1/ADC1/TRIAC Digital tristate I/O / 2 N.C. - 3)analogue input 3 RESET_N Digital input

3)

20 P0.0/ADC0/ZEROX Digital tristate I/O / 4 P1.7/INT1 Digital tristate I/O

analogue input 5 P1.6/PWM/INT0 Digital tristate I/O

21 (VSS) (Power) 6 P1.5 Digital tristate I/O

22 XOSC_Q2 Analogue output 7 P1.4/SCK Digital tristate I/O

23 XOSC_Q1 Analogue input 8 VPP Leave unconnected

24 AVDD_CO Power 9 P1.3/MOSI Digital tristate I/O

25 (VSS) (Power) 10 P1.3/MISO Digital tristate I/O

26 AVDD_SY Power 11 DVDD_IO Power

27 AVDD_RF Power 12 DVDD Power

28 TX_IND RF 13 MAIN Power

29 RF_IO RF Leave unconnected

30 RX_IND RF 14 DVDD Power

31 AVDD_IF Power 15 SUPP Power

4)

Leave unconnected 32 (VSS) Power, optional

16 DVDD Power NOTES

1)

Exposed pad at bottom of chip. 17 P1.1/ADC3/RXD Digital tristate I/O / 2)

No connect. Leave pin unconnected. analogue input 3)

4)

Schmitt trigger input.

VSS pins 21, 25 and 32 are internally connected to the exposed pad. Connection of these pins to ground is optional.

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5.3 Package Type and Outlines

The 200 and the 300 Series Z-Wave Single Chips are packed in a 32 pins QFN package with the following outlines:

Symbol Min. Nom. Max. Unit Remark A 0.90 mm Package height A1 0.00 0.01 0.05 mm A2 - 0.65 0.70 mm A3 0.20 mm b 0.18 0.23 0.30 mm D 5.00 mm D1 4.75 mm D2 3.15 3.30 3.45 mm E 5.00 mm Outer body size E1 4.75 mm E2 3.15 3.30 3.45 mm Exposed pad size L 0.30 0.40 0.50 mm e 0.50 mm Pin pitch

- θ1 0° 12°

R 0.09 - - Tolerances of form and position

aaa 0.10 bbb 0.10 ccc 0.05

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APL10312-7 Programming the 200 and 300 Series Z-Wave Single Chip Flash 2007-03-02

5.4 Device Marking

The 200 and the 300 Series Z-Wave Chips are marked as depicted in Figure 16. Note that the first text line is “ZW0301” for the 300 Series Z-Wave Chip.

Figure 16 Device marking

Marking Meaning

R Version number CCCC Date code (year, week) B Wafer lot code (identifier) P Package/test plant identification code

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6 REFERENCES

[1] [2] [3] [4]

Zensys, DSH10694, Datasheet, ZW0201 Extended Datasheet for Developers Kit v5.0x Zensys, DSH10822, Datasheet, ZW0301 Extended Datasheet for Developers Kit v5.0x Zensys, DSH10572, Datasheet, ZW0102 Short Form Datasheet 903500006 Zensys, INS10579, Instruction, Programming the ZW0102 Flash and Lock Bits

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APL10312-7 Programming the 200 and 300 Series Z-Wave Single Chip Flash 2007-03-02

APPENDIX A UPGRADING A ZW0102 PROGRAMMING DEVICE

This appendix describes the changes to be made to modify an existing ZW0102 ([3]) programming device to be compatible with the 200 and the 300 Series Z-Wave Single Chips Appendix A.1

Flash Memory

The flash program memory space is still 32k bytes, but the page size has increased from 128 bytes to 256 bytes. Hence, the number of flash pages has decreased from 256 to 128. The lock bit configuration is unchanged.

The possibility to store the 4 bytes Infodata in the flash has been added to the 200 and the 300 Series Z-Wave Single Chip. Appendix A.2

SPI Programming Hardware Interface

The bias resistor needed for the ZW0102 circuit is no longer applicable for the 200 or the 300 Series Z-Wave Single Chips.

To be able to enter programming mode the programming interface for the ZW0102 included a PROG_N signal, whereas the 200 and the 300 Series Z-Wave Single Chips use the RESET_N signal to enter programming mode. The SPI interface is unchanged.

The X-tal/clock signal circuit is unchanged, but note that the electrical specifications has changed, see section 5.1 Appendix A.3

Protocol and Instructions

The PROG_N pin must be asserted for enabling programming mode in ZW0102, whereas the RESET_N pin must be kept low for tPE to enter programming mode in the 200 and the 300 Series Z-Wave Single Chips.

The syntax of all the SPI programming instructions for the ZW0102 is unchanged except for the ‘Read Program Memory’, ‘Load Program Memory’, and ‘Write Program Memory Page’ instructions; the changes are caused by the change of flash page size.

The following instructions have been added to the SPI programming Instruction set of the 200 and the 300 Series Z-Wave Single Chips: ‘Program Memory Erase’, ‘Page Erase’, ‘Write Infodata’, and ‘Read Infodata’.

The signature consists of 6 bytes in the ZW0102 whereas the signature in the 200 and the 300 Series Z-Wave Single Chips consists of 7 bytes. Appendix A.4

Programming Sequence

The basic programming sequence is unchanged. The possibility to program/read the Infodata has been added. Appendix A.5

Programming Timing

Both the SPI timing and the SPI instruction timing have changed; compare the Programming Timing section in this document and [4]

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