STEP-LESS 3-DIMM CLOCK
W83194BR-39B
Step-less Frequency VIA PC/PM 133
Clock Gen. with S.S.T.
Date: May 24, 2005 Revision: A1
Publication Release Date: May 24, 2005
- I - Revision A1
W83194BR-39B
Table of Contents- 1. GENERAL DESCRIPTION.........................................................................................................1 2. PRODUCT FEATURES..............................................................................................................1 3. PIN CONFIGURATION...............................................................................................................2 4. BLOCK DIAGRAM......................................................................................................................2 5. PIN DESCRIPTION.....................................................................................................................3
5.1 Crystal I/O.................................................................................................................................3 5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs............................................................................3 5.3 I2C Control Interface................................................................................................................4 5.4 Fixed Frequency Outputs.........................................................................................................4 5.5 Power Pins................................................................................................................................4 6. MODE PIN -POWER MANAGEMENT INPUT CONTROL.........................................................5 7. FREQUENCY BY HARDWARE..................................................................................................5 8. FUNCTION DESCRIPTION........................................................................................................5
8.1 2-WIRE I2C CONTROL INTERFACE.....................................................................................5 8.2 SERIAL CONTROL REGISTERS...........................................................................................6
8.2.1 Register 0: CPU Frequency Select Register (default = 0)..............................................8 8.2.2 Register 1: CPU, 48/24 MHz Clock Register (1 = enable, 0 = Stopped)........................9 8.2.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped).............................................9 8.2.4 Register 3: SDRAM Clock Register (1 = enable, 0 = Stopped)......................................9 8.2.5 Register 4: Reserved Register (1 = enable, 0 = Stopped)...........................................10 8.2.6 Register 5: Reserved Register.....................................................................................10 8.2.7 Register 6: Watchdog Timer Register..........................................................................10 8.2.8 Register 7: M/N Program Register...............................................................................11 8.2.9 Register 8: M/N Program Register...............................................................................11 8.2.10 Register 9: Spread Spectrum Programming Register..................................................11 8.2.11 Register 10: Divisor and Step-less Enable Register....................................................12 8.2.12 Register 11: Winbond Chip ID Register (Read Only)................................................12 8.2.13 Register 12: Winbond Chip ID Register (Read Only)................................................12
9. SPECIFICATIONS....................................................................................................................13
9.1 ABSOLUTE MAXIMUM RATINGS.......................................................................................13 9.2 AC CHARACTERISTICS.......................................................................................................13 9.3 DC CHARACTERISTICS......................................................................................................14 9.4 BUFFER CHARACTERISTICS.............................................................................................14
9.4.1 TYPE 1 BUFFER FOR CPU CLOCK...........................................................................14 9.4.2 TYPE 2 BUFFER FOR IOAPIC....................................................................................15 9.4.3 TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ...........................................................15 9.4.4 TYPE 4 BUFFER FOR SDRAM (0:12)........................................................................15 9.4.5 TYPE 5 BUFFER FOR PCICLK (0:4,F).......................................................................16
10. OPERATION OF DUAL FUNCTION PINS...............................................................................16 11. ORDERING INFORMATION.....................................................................................................18 12. HOW TO READ THE TOP MARKING......................................................................................18 13. PACKAGE DRAWING AND DIMENSIONS..............................................................................18 14. REVISION HISTORY................................................................................................................19
- II -
W83194BR-39B
1. GENERAL DESCRIPTION
The W83194BR-39B is a Clock Synthesizer, which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel Pentium II or Pentium III. W83194BR-39B provides 64 CPU/PCI frequencies, which are selectable with smooth transitions by hardware or software. W83194BR-39B also provides 13 SDRAM clocks controlled by the none-delay buffer in pin.
The W83194BR-39B provides step-less frequency programming by controlling the VCO freq. and the programmable PCI clock output divisor ratio. A watchdog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.
The W83194BR-39B accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots (ISA, PCI, CPU, DIMM) is not recommend.
2. PRODUCT FEATURES
• Supports Pentium II and III CPU with I2C. • 2 CPU clocks (one free-running CPU clock) • 13 SDRAM clocks for 3 DIMMs • 6 PCI synchronous clocks
• One IOAPIC clock for multiprocessor support • Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 = 3.3V, VddL1 = VddL2 = 2.5V)
• < 250ps skew among CPU and SDRAM clocks • < 250ps skew among PCI clocks
• < 5ns propagation delay SDRAM from buffer input
• Skew from CPU (earlier) to PCI clock 1 to 4ns, center 2.6ns.
• Smooth frequency switch with selections from 66 MHz to 200 MHz CPU
• Step-less frequency programming by controlling the VCO freq. and the clock output divisor ratio • I2C 2-Wire serial interface and I2C read back
• ±0.25% or ±0.5% spread spectrum function to reduce EMI in freq. table mode • Programmable spread spectrum in the M/N step-less mode
• Programmable registers to enable/stop each output and select modes • MODE pin for power Management
• RESET# out when watch dog timer time out
• One 48 MHz for USB & one 24 MHz for super I/O • 48-pin SSOP package
Publication Release Date: May 24, 2005
- 1 - Revision A1
W83194BR-39B
3. PIN CONFIGURATION
Vddq1* PD#/REF0^VssXinXoutVddq2PCICLK_F/MODE0*PCICLK0^/FS3&VssPCICLK1^PCICLK2^PCICLK3^PCICLK4Vddq2BUFFER INVssSDRAM11SDRAM10Vddq3SDRAM 9SDRAM 8VssSDATA*SDCLK* 1 2 3 4 5 6 7 8 9101112131415161718192021222324484746454443424140393837363534333231302928272625VddL1IOAPICREF1/FS2*VssCPUCLK_FCPUCLK1VddL2RESET$SDRAM12VssSDRAM 0SDRAM 1Vddq3SDRAM 2SDRAM 3VssSDRAM 4SDRAM 5Vddq3SDRAM 6SDRAM 7Vddq448MHz/FS0*24MHz/FS1** :internal 120K pull-high &:Internal 120K pull-down^ :1.5X strength#: active low$ :open drain 4. BLOCK DIAGRAM
PLL2aXinXoutBUFFER INXTALOSC48MHz1/2STOP24MHzIOAPIC2REF(0:1)CPUCLK_F Spread SpectrumFS(0:3)*MODE*4LATCHPLL1STOPCPUCLK1SDRAM12STOP4PCIClock Divider12SDRAM(0:11)aPORCPU_STOP#PCI_STOP#SDATA*SDCLK*STOP5PCICLK(0:4)PCICLK_FControl LogicConfig. Reg. - 2 -
W83194BR-39B
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL
DESCRIPTION
IN Input OUT Output I/O Bi-directional Pin # Active Low & *
Internal 120KΩ pull-down Internal 120kΩ pull-up
5.1 Crystal I/O
PIN PIN NAME TYPE
DESCRIPTION
Crystal input with internal loading capacitors and
4 Xin IN feedback resistors.
5 Xout OUT Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
PIN PIN NAME TYPE
DESCRIPTION
OUT Free running CPU clock. Not affected by PD#
Low skew (< 250ps) clock outputs for host frequencies
43 CPUCLK1 OUT such as CPU, Chipset and Cache. Powered by VddL2.
Low if PD# is low.
RESET# (open drain, 4ms low active pulse when Watch
41 RESET# OD Dog time out)
High drive buffered output of the crystal, and is powered
47 IOAPIC OUT by VddL1.
17,18,20,21,2
SDRAM clock outputs. Fan out buffer outputs from
SDRAM [0:12] OUT 8,29,31,32,34
BUFFER IN pin. (Controlled by chipset)
, 35,37,38,40
PCICLK_F OUT Free running PCI clock during normal operation.
7 Latched Input. *Mode0=1, Pin 2 is REF0; *Mode0=0,
*MODE0 IN Pin2 is PD#
PCICLK0^ OUT Low skew (< 250ps) PCI clock outputs.
8 Latched input for FS3 at initial power up for H/W
FS3& IN selecting the output frequency of CPU and PCI clocks. Low skew (< 250ps) PCI clock outputs.
PCICLK [1:3]^
10,11,12,13 OUT PCICLK 0:3 are double strength pins
PCICLK 4
PCICLK 4 is not.
15 BUFFER IN IN Inputs to fan out for SDRAM outputs.
44 CPUCLK_F
Publication Release Date: May 24, 2005
- 3 - Revision A1
W83194BR-39B
5.3 I2C Control Interface
PIN PIN NAME TYPE DESCRIPTION
23 24
SDATA* SDCLK*
I/O IN
Serial data of I2C 2-wire control interface Serial clock of I2C 2-wire control interface
5.4 Fixed Frequency Outputs
PIN PIN NAME TYPE DESCRIPTION
2
14.318MHz reference clock. This REF output is the
REF0^ OUT stronger buffer for ISA bus loads.(pin7 *Mode0=1) Halt all clocks at logic 0 level, when input low (pin7
PD# IN *Mode0=0) REF1
OUT
14.318MHz reference clock.
Latched input for FS2 at initial power up for H/W
FS2* IN selecting the output frequency of CPU, SDRAM and PCI
clocks. 24MHz
OUT
24MHz output clock.
Latched input for FS1 at initial power up for H/W
FS1* I/O selecting the output frequency of CPU, SDRAM and PCI
clocks. 48MHz
OUT
48MHz output for USB during normal operation.
Latched input for FS0 at initial power up for H/W
FS0* IN selecting the output frequency of CPU, SDRAM and PCI
clocks.
46
25
26
5.5 Power Pins
PIN
PIN NAME
DESCRIPTION
1 48 42 6, 14 19, 30, 36
27 3,9,16,22,33,
39,45
Vddq1 VddL1 VddL2 Vddq2 Vddq3 Vddq4
Power supply for Ref [0:1] crystal and core logic. Power supply for IOAPIC output, either 2.5V or 3.3V. Power supply for CPUCLK [0:3], either 2.5V or 3.3V. Power supply for PCICLK_F, PCICLK [0:4], 3.3V.
Power supply for SDRAM [0:12], and CPU PLL core, nominal 3.3V.
Power for 24 & 48MHz output buffers and fixed PLL core.
Vss Circuit Ground.
- 4 -
W83194BR-39B
6. MODE PIN -POWER MANAGEMENT INPUT CONTROL
MODE0, PIN7 (LATCHED INPUT)
PIN 2
0 PD# (Input) 1 REF0 (Output) 7. FREQUENCY BY HARDWARE
FS3 FS2 FS1 FS0 CPU (MHZ)
PCI (MHZ)
0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 80.00 40.00
75.00 37.50 83.30 41.65
66.82 33.41 103.00 34.33 112.00 37.34 68.01 34.01 100.23 33.41 120.00 30.00 115.00 38.33 120.00 40.00 105.00 35.00 140.00 35.00 155.00 38.75 124.00 31.00 133.30 33.30
8. FUNCTION DESCRIPTION
8.1 2-WIRE I2C CONTROL INTERFACE
The clock generator is a slave I2C component, which can be read back the data, stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83194BR-39Binitializes with default register settings. Use of the 2-wire control interface is then optional.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Publication Release Date: May 24, 2005
- 5 - Revision A1
W83194BR-39B
Byte writing starts with a “start” condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an “acknowledge“ (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows:
Bytes sequence order for I2C controller:
Clock AddressA(6:0) & R/W
Ack
8 bits dummy Command code
Ack
8 bits dummy Byte count
Ack
Byte0,1,2...until Stop
Set R/W to 1 when read back”, the data sequence is as follows:
Clock AddressA(6:0) & R/W
AckByte 0AckByte 1
Ack
Byte2, 3, 4... until Stop
8.2 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the default state at true power up. \"Command Code\" byte and \"Byte Count” byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered \"don't care\(Register 0, Register 1, Register 2...) will be valid and acknowledged.
FREQUENCY BY SOFTWARE
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1SSEL0
CPU (MHZ)
PCI (MHZ)
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 80.00 40.00 75.00 37.50 83.30 41.65
66.82 33.41 103.00 34.33 112.00 37.34 68.01 34.01 100.23 33.41 120.00 30.00 115.00 38.33 120.00 40.00 105.00 35.00 140.00 35.00 155.00 38.75 124.00 31.00 133.30 33.30 160.00 40.00 127.00 31.75 - 6 -
W83194BR-39B
FREQUENCY BY SOFTWARE, continued.
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1SSEL0CPU (MHZ) PCI (MHZ)
0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 130.00 135.00 136.00 137.00 139.00 140.00 141.00 142.00 143.00 144.00 145.00 146.00 148.00 149.00 151.00 152.00 153.00 154.00 155.00 156.00 157.00 158.00 159.00 162.00 163.00 164.00 165.00 167.00 168.00 169.00 170.00 172.00 174.00 176.00 32.50 33.75 34.00 34.25 34.75 35.00 35.25 35.50 35.75 36.00 36.25 36.50 37.00 37.25 37.75 38.00 38.25 38.50 38.75 39.00 39.25 39.50 39.75 40.50 32.60 32.80 33.00 33.40 33.60 33.80 34.00 34.40 34.80 35.20 Publication Release Date: May 24, 2005
- 7 - Revision A1
W83194BR-39B
FREQUENCY BY SOFTWARE, continued.
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1SSEL0CPU (MHZ) PCI (MHZ)
1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 178.00 180.00 182.00 184.00 186.00 188.00 190.00 192.00 194.00 196.00 198.00 200.00 35.60 36.00 36.40 36.80 37.20 37.60 38.00 38.40 38.80 39.20 39.60 40.00 8.2.1 Register 0: CPU Frequency Select Register (default = 0)
BIT @POWERUP PIN
DESCRIPTION
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
- - - - - - - -
SSEL5 (for frequency table selection by software via I2C) SSEL4 (for frequency table selection by software via I2C) SSEL3 (for frequency table selection by software via I2C) SSEL2 (for frequency table selection by software via I2C) SSEL1 (for frequency table selection by software via I2C) SSEL0 (for frequency table selection by software via I2C) 0 = Selection by hardware
1 = Selection by software I2C - Bit 7:2 0 = Running
1 = Tristate all outputs
- 8 -
W83194BR-39B
8.2.2 Register 1: CPU, 48/24 MHz Clock Register (1 = enable, 0 = Stopped)
BIT @POWERUP PIN DESCRIPTION
7 1 - Reserved 6 1 - Reserved 5 4 3 1 0
0 0 1 1 1
- - 40 43 44
0 = Normal
1 = Spread Spectrum enabled
0 = ±0.25% Spread Spectrum Modulation 1 = ±0.5% Spread Spectrum Modulation SDRAM12 (Active / Inactive) CPUCLK1 (Active / Inactive) CPUCLK_F (Active / Inactive)
2 1 - Reserved
8.2.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)
BIT @POWERUP PIN DESCRIPTION
7 1 - Reserved 6
1
7
PCICLK_F (Active / Inactive)
5 1 - Reserved
4 1 14 PCICLK4 (Active / Inactive) 3 1 12 PCICLK3 (Active / Inactive) 2 1 11 PCICLK2 (Active / Inactive) 1
1
10
PCICLk1 (Active / Inactive)
0 1 8 PCICLK0 (Active / Inactive)
8.2.4 Register 3: SDRAM Clock Register (1 = enable, 0 = Stopped)
BIT @POWERUP PIN
DESCRIPTION
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
46 2 26 25 47 21,20,18,1732,31,29,2838,37,35,34
REF1 (Active / Inactive) REF0 (Active / Inactive) 48MHz (Active / Inactive) 24MHz (Active / Inactive) IOAPIC (Active / Inactive) SDRAM (8:11) (Active / Inactive) SDRAM (4:7) (Active / Inactive) SDRAM (0:3) (Active / Inactive)
Publication Release Date: May 24, 2005
- 9 - Revision A1
W83194BR-39B
8.2.5 Register 4: Reserved Register (1 = enable, 0 = Stopped)
BIT @POWERUP PIN DESCRIPTION
7 1 - Reserved 6 X - Latched FS3# 5 X - Latched FS2# 4 X - Latched FS1# 3 X - Latched FS0# 2 1 - Reserved 1 1 - Reserved 0 1 - Reserved
8.2.6 Register 5: Reserved Register
BIT @POWERUP PIN DESCRIPTION
7 1 - Reserved 6 0 - Reserved 5 0 - Reserved 4 1 - Reserved 3 0 - Reserved 2 0 - Reserved 1 1 - Reserved 0 1 - Reserved
8.2.7 Register 6: Watchdog Timer Register
BIT @POWERUP PIN DESCRIPTION
Enable Count 1 = start timer 7 0 - 0 = stop timer 6 5 4 3 2 1 0
0 0 0 0 0 0 0
- - - - - - -
Second timeout status (READ ONLY) Second count 5 Second count 4 Second count 3 Second count 2 Second count 1 Second count 0
- 10 -
W83194BR-39B
8.2.8 Register 7: M/N Program Register
BIT @POWERUP PIN DESCRIPTION
7 6 5 4 3 2 1 0
0 0 1 0 0 0 0 0
- - - - - - - -
N value bit 8
Test 1(Please do not modify) Test 0 (Please do not modify) M value bit 4 M value bit 3 M value bit 2 M value bit 1 M value bit 0
8.2.9 Register 8: M/N Program Register
BIT @POWERUP PIN DESCRIPTION
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
- - - - - - - -
N value bit 7 N value bit 6 N value bit 5 N value bit 4 N value bit 3 N value bit 2 N value bit 1 N value bit 0
8.2.10 Register 9: Spread Spectrum Programming Register
BIT @POWERUP PIN DESCRIPTION
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
- - - - - - - -
Spread spectrum up count 3 Spread spectrum up count 2 Spread spectrum up count 1 Spread spectrum up count 0 Spread spectrum down count 3 Spread spectrum down count 2 Spread spectrum down count 1 Spread spectrum down count 0
Publication Release Date: May 24, 2005
- 11 - Revision A1
W83194BR-39B
8.2.11 Register 10: Divisor and Step-less Enable Register
BIT @POWERUP PIN DESCRIPTION
0: use frequency table 7 0 - 1: use M/N register to program frequency
The equation is VCO freq. = 14.318MHz * (N+4)/2M
6 0 - Reserved
PCI Ratio SEL2 0,0,0 = 2
5 X - 0,0,1 = 3 PCI Ratio SEL1 0,1,0 = 4
4 X - 0,1,1 = 5 PCI Ratio SEL0 1,0,0 = 6
3 X - 1,0,1…= X
2 0 - Reserved 1 0 - Reserved 0 0 - Reserved
8.2.12 Register 11: Winbond Chip ID Register (Read Only)
BIT @POWERUP PIN DESCRIPTION
7 0 - Winbond Chip ID 6 1 - Winbond Chip ID 5 1 - Winbond Chip ID 4 0 - Winbond Chip ID 3 0 - Winbond Chip ID 2 0 - Winbond Chip ID 1 1 - Winbond Chip ID 0 0 - Winbond Chip ID
8.2.13 Register 12: Winbond Chip ID Register (Read Only)
BIT @POWERUP PIN DESCRIPTION
7 6 5 4 3 2 1 0
0 - Winbond Chip ID 1 - Winbond Chip ID 0 - Winbond Chip ID 1 - Winbond Chip ID 0 0 0 1
- - - -
Winbond Version ID Winbond Version ID Winbond Version ID Winbond Version ID
- 12 -
W83194BR-39B
9. SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
Voltage on any pin with respect to GND
Storage Temperature Ambient Temperature Operating Temperature
- 0.5 V to + 7.0 V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C
SYMBOL PARAMETER RATING Vdd VIN TSTG TB TA
9.2 AC CHARACTERISTICS
Vdd = Vddq3 = 3.3V ± 5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V, TA = 0°C to +70°C
PARAMETER SYMBOLMIN
TYP
MAX
UNITS
TEST CONDITIONS Output Duty Cycle CPU/SDRAM to PCI Offset Skew (CPU-CPU), (PCI-PCI), (SDRAM-SDRAM) CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) & Fall (2.0V ~0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion
tOFF tSKEW tCCJ tJA BWJ tTLH tTHL Vover VRBE
45 50 55 % Measured at 1.5V
15 pF Load Measured
1 2.6 4 ns at 1.5V 15 pF Load Measured
250 ps at 1.5V ±250
ps
500 ps 500 KHz
15 pF Load on CPU 0.4 1.6 ns and PCI outputs 22 Ω at source of 8
0.7 1.5 V inch PCB run to 15 pF
load Ring Back must not
0.7 2.1 V enter this range.
Publication Release Date: May 24, 2005
- 13 - Revision A1
W83194BR-39B
9.3 DC CHARACTERISTICS
Vdd = Vddq3 = 3.3V ± 5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V, TA = 0°C to +70°C
PARAMETER SYMBOLMIN
TYP
MAX
UNITS
TEST CONDITIONS Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 4 mA
Output High Voltage IOH = 4mA
Tri-State leakage Current Dynamic Supply Current for Vdd + Vddq3 Dynamic Supply Current for Vddq2 + Vddq2b CPU Stop Current for Vdd + Vddq3 CPU Stop Current for Vddq2 + Vddq2b PCI Stop Current for Vdd + Vddq3
VIL VIH IIL IIH VOL VOH Ioz Idd3 Idd2 ICPUS3 ICPUS2 IPD3
0.8 Vdc 2.0
Vdc
-66 µA 5 µA 0.4 Vdc 2.4
Vdc
All outputs
All outputs using 3.3V
power
10 µA CPU = 66.6 MHz
mA PCI = 33.3 Mhz with
load
Same as above
mA
Same as above
mA
Same as above
mA
mA
9.4 BUFFER CHARACTERISTICS
9.4.1 TYPE 1 BUFFER FOR CPU CLOCK
PARAMETER SYMBOLMIN
TYP
MAX
UNITS
TEST CONDITIONS Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max
Rise/Fall Time Min
Between 0.4 V and 2.0 V Rise/Fall Time Max
Between 0.4 V and 2.0 V
IOH (min) IOH (max)IOL (min) IOL (max) TRF (min)TRF (max)
-27
-27 27
mA mA mA mA
Vout = 1.0 V Vout = 2.0V Vout = 1.2 V Vout = 0.3 V
0.4 ns 10pF Load 1.6 ns 20pF Load
- 14 -
W83194BR-39B
9.4.2 TYPE 2 BUFFER FOR IOAPIC
PARAMETER SYMBOLMIN TYP MAX
UNITS
TEST CONDITIONS Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min
Between 0.7 V and 1.7 V Rise/Fall Time Max
Between 0.7 V and 1.7 V
IOH (min)IOH (max)IOL (min)IOL (max) TRF (min)TRF (max)
-29 28
mA mA mA mA
Vout = 1.4 V Vout = 2.7 V Vout = 1.0 V Vout = 0.2 V
0.4 ns 10pF Load 1.8 ns 20pF Load
9.4.3 TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ
PARAMETER SYMBOLMIN
TYP
MAX
UNITS TEST CONDITIONS Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min
Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V
IOH (min) IOH (max) IOL (min) IOL (max) TRF (min) TRF (max)
-29 29
-23
mA mA mA mA
Vout = 1.0 V Vout = 3.135V Vout = 1.95 V Vout = 0.4 V
1.0 ns 10pF Load 4.0 ns 20pF Load
9.4.4 TYPE 4 BUFFER FOR SDRAM (0:12)
PARAMETER SYMBOLMIN
TYP
MAX
UNITS TEST CONDITIONS Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min
Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V
IOH (min) IOH (max) IOL (min) IOL (max) TRF (min) TRF (max)
-46 53
mA mA mA mA
Vout = 1.65 V Vout = 3.135 V Vout = 1.65 V Vout = 0.4 V
0.5 ns 20pF Load 1.3 ns 30pF Load
Publication Release Date: May 24, 2005
- 15 - Revision A1
W83194BR-39B
9.4.5 TYPE 5 BUFFER FOR PCICLK (0:4,F)
PARAMETER SYMBOLMIN
TYP
MAX
UNITS TEST CONDITIONS Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min
Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V
IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max)
-33 30
-33 38
mA mA mA mA
Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V
0.5 ns 15pF Load 2.0 ns 30pF Load
10. OPERATION OF DUAL FUNCTION PINS
Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore, and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these pins is latched into their appropriate internal registers. Once the correct information is properly latched, these pins will change into output pins and will be pulled low by default. At the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
2.5VVdd#7 PCICLK_F/MODE#46 REF1/FS2#25 24/FS1#26 48/FS0Output tri-stateOutput pull-lowWithin 3msInputAll other clocksOutput tri-stateOutputOutput pull-low Each of these pins has a large pull-up resistor (250 kΩ @3.3V) inside. The default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 kΩ resistor is recommended to be connected to Vdd if logic 1 is expected. Otherwise, there should be direct connection to ground if a logic 0 is desired. The 10 kΩ resistor should be placed before the serious terminating resistor. Note that this logic will only be latched at initial power on.
If optional EMI reducing capacitors are needed, they should be placed as close to the series terminating resistor as possible and after the series-terminating resistor. These capacitors have typical values ranging from 4.7pF to 22pF.
- 16 -
W83194BR-39B
OPERATION of dual function pins, continued.
Vdd10kΩDevicePin10kΩSeriesTerminatingResistorClock TraceEMI Reducing CapOptionalGroundGround
Programming HeaderVdd Pad10kΩDevice PinGround PadSeriesTerminatingResistorClock TraceEMI ReducingCapOptionalGround Publication Release Date: May 24, 2005
- 17 - Revision A1
W83194BR-39B
11. ORDERING INFORMATION
PART NUMBER
PACKAGE TYPE
PRODUCTION FLOW
W83194BR-39B 48 PIN SSOP Commercial, 0°C to +70°C
12. HOW TO READ THE TOP MARKING
1st line: Winbond logo and the type number: W83194BR-39B 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number
3rd line: Tracking code 814 G B B
814: packages made in '98, week 14
G: assembly house ID; A means ASE, S means SPIL, G means GR B: Winbond internal use code A: IC revision
W83194BR-39B28051234 814GBA All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
13. PACKAGE DRAWING AND DIMENSIONS
- 18 -
W83194BR-39B
14. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
1.0 2.0 A1
02/Apr 2/18/03 May 24, 2005
n.a. n.a. All 19
All of the versions before 0.50 are for internal use.
Change version and version on web site to 1.0
Update new form ADD Important Notice
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,Hsinchu, TaiwanTEL: 886-3-5770066FAX: 886-3-5665577
http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose,CA 95134, U.S.A.TEL: 1-408-9436666FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China
TEL: 86-21-62365999FAX: 86-21-62365998
Taipei OfficeWinbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033TEL: 81-45-4781881FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong KongTEL: 852-27513100FAX: 852-27552064
9F, No.480, Rueiguang Rd.,Neihu District, Taipei, 114,Taiwan, R.O.C.
TEL: 886-2-8177-7168FAX: 886-2-8751-3579
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Publication Release Date: May 24, 2005
- 19 - Revision A1
因篇幅问题不能全部显示，请点此查看更多更全内容