专利名称：Flip chip interconnection pad layout发明人：Rajendra D. Pendse申请号：US11372989申请日：20060310
公开号：US20060163715A1公开日：20060727
专利附图：
摘要：A flip chip interconnect pad layout has the die signal pads are arranged on thedie surface near the perimeter of the die, and the die power and ground pads arrangedon the die surface inboard from the signal pads; and has the signal pads on the
corresponding package substrate arranged in a manner complementary to the die pad
layout and the signal lines routed from the signal pads beneath the die edge away fromthe die footprint, and has the power and ground lines routed to vias beneath the diefootprint. Also, a flip chip semiconductor package in which the flip chip interconnect padlayouts have the die signal pads situated in the marginal part of the die and the diepower and ground pads arranged on the die surface inboard from the signal pads, andthe corresponding package substrates have signal pads arranged in a mannercomplementary to the die pad layout and signal lines routed from the signal padsbeneath the die edge away from the die footprint.
申请人：Rajendra D. Pendse
地址：Fremont CA US
国籍：US
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