Latch and D-type flip-flop

专利名称：Latch and D-type flip-flop发明人：Koji, Hirairi申请号：EP01402480.6申请日：20010927公开号：EP1193871B1公开日：20061102

摘要：A latch and a D-type flip-flop capable of realizing high speed operation andcapable of achieving a reduction of power consumption, wherein in a master side latch, afirst NMOS transistor (NT116) always in the ON state is provided as a first parallelresistor means connected in parallel with a second NMOS transistor (NT113) (servicing asthe first input discriminating means) receiving a data input signal D, and a third NMOStransistor (NT117) always in the ON state is provided as a second parallel resistor meansconnected in parallel with a fourth NMOS transistor (NT114) (servicing as the secondinput discriminating means) receiving an inverted data input signal (DX). By this, withoutenlarging the transistor sizes of the second and fourth NMOS transistors, an equivalentcombined resistance of discharge paths can be reduced by these parallel resistor means,a high speed operation can be realized, and a lowering of a power consumption can berealized.

申请人：SONY CORP

地址：JP

国籍：JP

代理机构：Thévenet, Jean-Bruno

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