SN74ALS23664 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORYSDAS107C – OCTOBER 1986 – REVISED APRIL 1998DDDDD Asynchronous OperationOrganized as 64 Words by 4 BitsData Rates up to 30 MHz3-State OutputsPackage Options Include PlasticSmall-Outline Package (DW), PlasticJ-Leaded Chip Carriers (FN), and StandardPlastic 300-mil DIPs (N)DW OR N PACKAGE(TOP VIEW)descriptionThe SN74ALS236 is a 256-bit memory utilizingadvanced low-power Schottky IMPACT™technology. It features high speed with fastfall-through times and is organized as 64 words by4 bits.A first-in, first-out (FIFO) memory is a storagedevice that allows data to be written into and readfrom its array at independent data rates. TheSN74ALS236 is designed to process data at ratesup to 30 MHz in a bit-parallel format, word byword.NCIRSID0D1D2D3GND12345678161514131211109VCCSOORQ0Q1Q2Q3RSTFN PACKAGE(TOP VIEW)IRNCNCVCCSOSID0NCD1D24567832120191817161514910111213ORQ0NCQ1Q2Data is written into memory on the rising edge ofthe shift-in (SI) input. When SI goes low, the firstdata word ripples through to the output (seeFigure 1). As the FIFO fills up, the data wordsNC – No internal connectionstack up in the order they were written. When theFIFO is full, additional shift-in pulses have noeffect. Data is shifted out of memory on the fallingedge of the shift-out (SO) input (see Figure 2). When the FIFO is empty, additional SO pulses have no effect.The last data word remains at the outputs until a new word falls through or reset (RST) goes low.Status of the SN74ALS236 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags.When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFOis empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low whenthe FIFO is full.When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held highduring this time, the OR flag pulses high, indicating valid data at the outputs (see Figure 3).When the FIFO is full, data is shifted in automatically by holding SI high and taking SO low. One propagationdelay after SO goes low, IR goes high. If SI is still high when IR goes high, data at the inputs is automaticallyshifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on theIR output (see Figure 4).D3GNDNCRSTQ3Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.IMPACT is a trademark of Texas Instruments Incorporated.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 1998, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1芯天下--http://oneic.com/SDAS107C – OCTOBER 1986 – REVISED APRIL 1998SN74ALS23664 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORYdescription (continued) The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR highand OR low, signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (seeFigure 1). If SI is high when RST goes high, the input data is shifted in and IR goes low and remains low untilSI goes low. If SI goes low before RST goes high, the input data is not shifted in and IR goes high. Data outputsare noninverting with respect to the data inputs.The SN74ALS236 is characterized for operation from 0°C to 70°C.logic symbol†FIFO 64 × 4315CTR5 + /C1G24 –G3CT = 0RSTD0D1D2D394567R1D13121110Q0Q1Q2Q32CT < 64(CT < 64) G53CT > 0(CT > 0) G42IR14SISOOR†This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.Pin numbers shown are for the DW and N packages.functional block diagramD0D1D2D3456713121110Q0Q1Q2Q3FIFOInputStage62 × 4 BitRegisterFIFOOutputStageIRSIRST239Input-ControlLogicRegister-ControlLogicOutput-ControlLogic1514SOORPin numbers shown are for the DW and N packages.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/ logic diagram (positive logic)POST OFFICE BOX 655303 DALLAS, TEXAS 752653D0Word 64Word 63Word 3Word 2Word 1stupnI aQ0stutaptDD1uOD2Q1Q2 atD3Q3aDWords 4 – 62Same as 3 or 63RSTSOORSIIR芯天下--http://oneic.com/SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY64 × 4SN74ALS236•SDAS107C – OCTOBER 1986 – REVISED APRIL 1998SN74ALS23664 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORYtiming diagramRST SID3–D0W1W2Don’t CareW1W2W63W64W1SOQ3–Q0Word 1Word 2Invalid†Word 1‡Word 2Word 3IRORClearShift InW1Shift OutW2EmptyFull†The last data word shifted out of the FIFO remains at the output until a new word falls through or an RST pulse clears the FIFO.‡While the output data is considered valid only when the OR flag is high, the stored data remains at the outputs. Any additional words writteninto the FIFO stack up behind the first word and do not appear at the output until SO is taken low.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/ SN74ALS23664 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORYSDAS107C – OCTOBER 1986 – REVISED APRIL 1998RSTtsuSItsuD3–D0thtPLHIRFulltPHLORtpdQ3–Q0NOTE A:SO is low.EmptytpdtPLHtPHLtPLHFigure 1. Master Reset and Data-In WaveformsSOtPLHORtPLHIRFulltd(SOL-QX)Q3–Q0tpdNOTE A:SI is low.tPHLFigure 2. Data-Out WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5芯天下--http://oneic.com/SDAS107C – OCTOBER 1986 – REVISED APRIL 1998SN74ALS23664 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORYD3–D0 tsuSIthSOtPLHtwOREmptytd(QV-ORH)Q3–Q0InvalidFigure 3. Data Fall-Through WaveformsSOSItPLHtwFullIRFullD3–D0Figure 4. Automatic Data-In Waveformsabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VInput voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VPackage thermal impedance, θJA (see Note 2):DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105°C/WFN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/WN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/WStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.All voltage values are with respect to GND.2.The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a tracelength of zero.6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/ SN74ALS23664 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORYSDAS107C – OCTOBER 1986 – REVISED APRIL 1998recommended operating conditionsMINVCCVIHVILIOHIOLTASupply voltageHigh-level input voltageLow-level input voltageHighleveloutputcurrentHigh-level output currentLowleveloutputcurrentLow-level output currentOperating free-air temperatureQ outputsIR and ORQ outputsIR and OR04.520.8– 2.6– 0.424870NOM5MAX5.5UNITVVVmAmA°Celectrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERVIKVOHAnyQAny QIR, ORAnyQAny QVOLIRORIR, ORIIIIHIILIO‡ICC=45VVCC = 4.5 VVCC = 5.5 V,VCC = 5.5 V,VCC = 5.5 V,VCC = 5.5 V,VCC = 5.5 V=55VVCC = 4.5 V,=45VVCC = 4.5 VVCC = 4.5 V,VCC = 4.5 V=45VTEST CONDITIONSII = –18 mAIOH = –1 mAIOH = –2.6 mAIOH = –0.4 mAIOL = 12 mAIOL = 24 mAIOL = 4 mAIOL = 8 mAVI = 7 VVI = 2.7 VVI = 0.4 VVO = 2.25 VLowHigh–30100972.42.73.23.40.250.350.250.350.40.50.40.50.120–0.1–112145142mAµAmAmAmAVMINTYP†MAX–1.2UNITVV†All typical values are at VCC = 5 V, TA = 25°C.‡The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.timing requirements over recommended operating conditions (unless otherwise noted) (seeFigure 5)MINfclocktwClock frequencyPulsedurationPulse durationSI or SOSI or SORSTDatatsuthSetup time before SI↑Hold time, data after SI↑RSTHigh(inactive)High or lowLow151501517nsnsMAX30UNITMHznsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7芯天下--http://oneic.com/SDAS107C – OCTOBER 1986 – REVISED APRIL 1998SN74ALS23664 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORYswitching characteristics (see Figure 5)PARAMETERfmaxtw‡tw§td(QV-ORH)td(SOL-QX)tpdtPHLtPLHtPLH¶tpdtPHLtPLHtPLH¶tPHLtPLHtPHLSI↓SI↑SI↓SI↓SO↓SO↑SO↓SO↓RST↓RST↓FROM(INPUT)SISOIR highOR highQ valid before OR↑Q valid after SO↓QIRORQORIRORIRQ14TO(OUTPUT)MINTYP†35351519613600201660013232060022171480026218001727248002621179MAXMIN303088–54350863504763501065100030251000223330100034271912MAXUNITMHznsnsnsnsnsnsnsnsnsnsnsns †All typical values are at VCC = 5 V, TA = 25°C.‡The IR output pulse occurs when the FIFO is full, SI is high, and SO is pulsed (see Figure 4).§The OR output pulse occurs when the FIFO is empty, SO is high, and SI is pulsed (see Figure 3).¶Data throughput or fall-through times8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/ SN74ALS23664 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORYSDAS107C – OCTOBER 1986 – REVISED APRIL 1998PARAMETER MEASUREMENT INFORMATION7 VOpenS1R1 = 500 ΩFrom OutputUnder TestCL = 50 pF(see Note A)Test PointR2 = 500 ΩPARAMETERtentdistpdtPZHtPZLtPHZtPLZtPLHtPHLS1OpenClosedOpenClosedOpenOpenLOAD CIRCUIT FOR 3-STATE OUTPUTSHigh-LevelPulseTimingInputtsuDataInput1.3 V3.5 V1.3 Vth1.3 V0.3 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESOutputControlInput(see Note C)tPLHIn-PhaseOutputtPHLOut-of-PhaseOutput1.3 V3.5 V1.3 V1.3 V0.3 VtPHL1.3 VVOH1.3 VVOLtPLH1.3 VVOHVOLVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESWaveform 2S1 Open(see Note B)Waveform 1S1 Closed(see Note B)tPZH1.3 VtPZLtPLZ1.3 V1.3 V0.3 V3.5 VLow-LevelPulse1.3 Vtw1.3 V3.5 V0.3 V3.5 V1.3 V1.3 V0.3 VVOLTAGE WAVEFORMSPULSE DURATION3.5 V0.3 V3.5 VtPHZVOL0.3 VVOH1.3 V0.3 V0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, 3-STATE OUTPUTSNOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 2 ns, tf≤ 2 ns.D.The outputs are measured one at a time with one transition per measurement.Figure 5. Load Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•9芯天下--http://oneic.com/SDAS107C – OCTOBER 1986 – REVISED APRIL 1998SN74ALS23664 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORYAPPLICATION INFORMATION IRSID0D1D2D3RSTSOORQ0Q1Q2Q3IRSID0D1D2D3RSTSOORQ0Q1Q2Q3IRSID0D1D2D3RSTSOORQ0Q1Q2Q3SOIRIRSID0D1D2D3RSTSOORQ0Q1Q2Q3IRSID0D1D2D3RSTSOORQ0Q1Q2Q3IRSID0D1D2D3RSTSOORQ0Q1Q2Q3ORIRSISID0D1D2D3RSTSOORQ0Q1Q2Q3IRSID0D1D2D3RSTSOORQ0Q1Q2Q3IRSID0D1D2D3RSTSOORQ0Q1Q2Q3RSTFigure 6. Word-Width Expansion: 192 × 12 Bits10POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/PACKAGEOPTIONADDENDUM
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22-Sep-2008
PACKAGINGINFORMATION
OrderableDeviceSN74ALS236N
(1)
Status(1)ACTIVE
PackageTypePDIP
PackageDrawing
N
PinsPackageEcoPlan(2)
Qty16
25
Pb-Free(RoHS)
Lead/BallFinishCUNIPDAU
MSLPeakTemp(3)N/AforPkgType
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
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