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AD9268

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16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual

FEATURES

SNR = 78.2 dBFS @ 70 MHz and 125 MSPS

SFDR = 88 dBc @ 70 MHz and 125 MSPS Low power: 750 mW @ 125 MSPS 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply Integer 1-to-8 input clock divider IF sampling frequencies to 300 MHz

−153.6 dBm/Hz small-signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS Optional on-chip dither

Programmable internal ADC voltage reference Integrated ADC sample-and-hold inputs

Flexible analog input range: 1 V p-p to 2 V p-p

Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control

User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems

General-purpose software radios Broadband data applications Ultrasound equipment

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Analog-to-Digital Converter (ADC)

AD9268

FUNCTIONAL BLOCK DIAGRAM

AVDDSDIO/SCLK/DCSDFSCSBDRVDDAD9268SPIPROGRAMMING DATAORAVIN+ACMOS/LVDSD15A (MSB)VIN–AADC16OUTPUT BUFFERTOD0A (LSB)VREFDIVIDE 1CLK+TO 8SENSECLK–DUTY CYCLEDCODCOAREFSTABILIZERGENERATIONVCMSELECTDCOBRBIASORBVIN–BADCCMOS/LVDS16D15B (MSB)VIN+BOUTPUT BUFFERTOD0B (LSB)MULTICHIPSYNCAGNDSYNCPDWNOEBNOTES1001. PIN NAMESARE FOR THE CMOS PIN CONFIGURATION ONLY;-32 SEE FIGURE 7 FORLVDS PIN NAMES.180

Figure 1.

PRODUCT HIGHLIGHTS

1. On-chip dither option for improved SFDR performance with low power analog input.

2. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz.

Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs.

Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode.

Pin compatibility with the AD9258, allowing a simple

migration from 16 bits to 14 bits. The AD9268 is also pin compatible with the AD9251, AD9231, and AD9204 family of products for lower sample rate, low power applications.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com http://www.BDTIC.com/ADI

AD9268

Clock Input Considerations ...................................................... 30 Channel/Chip Synchronization ................................................ 31 Power Dissipation and Standby Mode .................................... 32 Digital Outputs ........................................................................... 32 Timing ......................................................................................... 33 Built-In Self-Test (BIST) and Output Test .................................. 34 Built-In Self-Test (BIST) ............................................................ 34 Output Test Modes ..................................................................... 34 Serial Port Interface (SPI) .............................................................. 35 Configuration Using the SPI ..................................................... 35 Hardware Interface ..................................................................... 36 Configuration Without the SPI ................................................ 36 SPI Accessible Features .............................................................. 36 Memory Map .................................................................................. 37 Reading the Memory Map Register Table ............................... 37 Memory Map Register Table ..................................................... 38 Memory Map Register Descriptions ........................................ 40 Applications Information .............................................................. 41 Design Guidelines ...................................................................... 41 Outline Dimensions ....................................................................... 42 Ordering Guide .......................................................................... 42

TABLE OF CONTENTS

Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 ADC DC Specifications ............................................................... 4 ADC AC Specifications ................................................................. 6 Digital Specifications ................................................................... 7 Switching Specifications ................................................................ 9 Timing Specifications ................................................................ 10 Absolute Maximum Ratings .......................................................... 12 Thermal Characteristics ............................................................ 12 ESD Caution ................................................................................ 12 Pin Configurations and Function Descriptions ......................... 13 Typical Performance Characteristics ........................................... 17 Equivalent Circuits ......................................................................... 25 Theory of Operation ...................................................................... 26 ADC Architecture ...................................................................... 26 Analog Input Considerations .................................................... 26 Voltage Reference ....................................................................... 29

REVISION HISTORY

9/09—Rev. 0 to Rev. A

Changes to Features List .................................................................. 1

Changes to Specifications Section .................................................. 4 Changes to Table 5 .......................................................................... 10 Changes to Typical Performance Characteristics Section ......... 17 5/09—Revision 0: Initial Version

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AD9268

The ADC output data can be routed directly to the two external 16-bit output ports. These outputs can be set to either 1.8 V CMOS or LVDS.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.

The AD9268 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

GENERAL DESCRIPTION

The AD9268 is a dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC). The AD9268 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

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AD9268

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1.

AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 GParameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 16 16 16 Bits ACCURACY No Missing Codes Full Guaranteed uaranteed uaranteed Offset Error Full ±0.2 ±0.4 ±0.2 ±0.5 ±0.4 ±0.65 % FSR ain Error Full ±0.4 ±2.5 ±0.4 ±2.5 ±0.4 ±2.5 % FSR

Full −1.0 +1.4 −1.0 +1.3 −1.0 +1.2 LSB GDifferential

Nonlinearity (DNL) 25°C ±0.65 ±0.7 ±0.7 LSB G

±4.5 ±5.1 ±5.5 LSB Integral Nonlinearity Full

(INL)1

25°C ±2.0 ±3.0 ±3.0 LSB

MATCHING

CHARACTERISTIC Offset Error Full ±0.1 ±0.4 ±0.1 ±0.4 ±0.2 ±0.45 % FSR Gain Error Full ±0.3 ±1.3 ±0.3 ±1.3 ±0.3 ±1.3 % FSR TEMPERATURE DRIFT G G Offset Error Full ±2 ±2 ±2 ppm/°C ain Error Full ±15 ±15 ±15 ppm/°C

INTERNAL VOLTAGE

REFERENCE

±5 ±12 ±5 ±12 ±5 ±12 mV Output Voltage Error Full

(1 V Mode)

Full 5 5 5 mV Load Regulation @

1.0 mA INPUT REFERRED NOISE VREF = 1.0 V 25°C 2.17 2.23 2.27 LSB

rms

ANALO INPUT

Full 2 2 2 V p-p Input Span, VREF =

1.0 V

Input Capacitance2Full 8 8 8 pF

Full 0.9 0.9 0.9 V Input Common-Mode Voltage

Full 6 6 6 kΩ REFERENCE INPUT

RESISTANCE POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current

IAVDDFull 234 240 293 300 390 400 mA

Full 35 45 55 mA IDRVDD1 (1.8 V

CMOS)

Full 89 89 94 mA IDRVDD1 (1.8 V

LVDS)

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AD9268

AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit POWER CONSUMPTION DC Input Full 420 450 565 590 750 777 mW

Full 485 608 800 mW Sine Wave Input

(DRVDD = 1.8 V CMOS Output Mode)

Full 582 685 870 mW Sine Wave Input1

(DRVDD = 1.8 V LVDS Output Mode)

Standby Power3Full 45 45 45 mW Power-Down Power Full 0.5 2.5 0.5 2.5 0.5 2.5 mW

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3

Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

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AD9268

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2.

AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125

ParameterTemp Min Typ Max Min Typ Max Min Typ Max Unit SINAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz 25°C 79.7 78.9 78.8 dBFS fIN = 70 MHz 25°C 78.3 79.0 77.2 78.8 77.2 78.2 dBFS Full 78.0 77.1 76.5 dBFS fIN = 140 MHz 25°C 77.4 76.9 77.1 dBFS fIN = 200 MHz 25°C 75.5 75.0 75.5 dBFS SINAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 2.4 MHz 25°C 79.4 78.3 78.3 dBFS fIN = 70 MHz 25°C 78.1 78.5 77.1 78.6 76.8 77.7 dBFS Full 77.7 76.8 76.2 dBFS fIN = 140 MHz 25°C 75.4 75.9 75.8 dBFS fIN = 200 MHz 25°C 74.3 72.2 74.0 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz 25°C 12.9 12.7 12.7 Bits fIN = 70 MHz 25°C 12.8 12.7 12.6 Bits f = 140 MHz 25°C 12.2 12.3 12.3 Bits GIN

fIN = 200 MHz 25°C 12.0 11.7 12.0 Bits WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz 25°C −92 −87 −90 dBc 25°C −91 −88 −93 −87 −88 −85 dBc GfIN = 70 MHz

Full −87 −87 −84 dBc fIN = 140 MHz 25°C −80 −84 −83 dBc fIN = 200 MHz 25°C −82 −77 −79 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz 25°C 92 87 90 dBc fIN = 70 MHz 25°C 88 91 87 93 85 88 dBc Full 87 87 84 dBc fIN = 140 MHz 25°C 80 84 83 dBc fIN = 200 MHz 25°C 82 77 79 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) Without Dither (AIN@ −23 dBFS) fIN = 2.4 MHz 25°C 93 100 88 dBFS fIN = 70 MHz 25°C 95 96 89 dBFS fIN = 140 MHz 25°C 98 96 90 dBFS fIN = 200 MHz 25°C 102 100 89 dBFS With On-Chip Dither (AIN @ −23 dBFS)

fIN = 2.4 MHz 25°C 107 106 106 dBFS fIN = 70 MHz 25°C 107 109 106 dBFS fIN = 140 MHz 25°C 106 104 104 dBFS fIN = 200 MHz 25°C 104 108 105 dBFS Rev. A | Page 6 of 44

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AD9268

AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125

ParameterTemp Min Typ Max Min Typ Max Min Typ Max Unit WORST OTHER (HARMONIC OR SPUR) Without Dither fIN = 2.4 MHz 25°C −99 −100 −100 dBc fIN = 70 MHz 25°C −100 −96 −99 −94 −100 −94 dBc Full −96 −94 −94 dBc fIN = 140 MHz 25°C −98 −98 −98 dBc fIN = 200 MHz 25°C −96 −94 −96 dBc With On-Chip Dither

fIN = 2.4 MHz 25°C −108 −107 −108 dBc fIN = 70 MHz 25°C −106 −96 −107 −95 −106 −95 dBc Full −96 −95 −95 dBc fIN = 140 MHz 25°C −105 −104 −103 dBc fIN = 200 MHz 25°C −102 −102 −99 dBc TWO-TONE SFDR, WITHOUT DITHER

fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS) 25°C 93 92 90 dBc fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS) 25°C 81 80 82 dBc

CROSSTALKFull −95 −95 −95 dB GANALO INPUT BANDWIDTH 25°C 650 650 650 MHz 12

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3.

Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ

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AD9268

Parameter Temperature Min Typ Max Unit

LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK/DFS) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT/OUTPUT (SDIO/DCS)1 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF LOGIC INPUTS (OEB, PDWN)2 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage IOH = 50 μA Full 1.79 V IOH = 0.5 mA Full 1.75 V Low Level Output Voltage IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Full 290 345 400 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 160 200 230 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V

Pull up. Pull down.

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AD9268

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4.

AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate1 DCS Enabled Full 20 80 20 105 20 125 MSPS DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 12.5 9.5 8 ns CLK Pulse Width High (tCH)

3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 Divide-by-1 Mode, DCS Enabled Full 5.6 ns 5.95 6.25 6.55 4.5 4.75 5.0 Divide-by-1 Mode, DCS Disabled Full 3.8 4 4.2 ns 0.8 0.8 ns Divide-by-2 Mode Through Divide-Full 0.8 by-8 Mode

Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.07 0.07 0.07 ps rms

DATA OUTPUT PARAMETERS CMOS Mode

2.8 4.2 2.8 3.5 4.2 Data Propagation Delay (tPD) Full 3.5 2.8 3.5 4.2 ns 2 DCO Propagation Delay (tDCO) Full 3.1 3.1 3.1 ns

DCO to Data Skew (tSKEW) Full −0.6 −0.4 0 −0.6 −0.4 0 −0.6 −0.4 0 ns LVDS Mode Data Propagation Delay (tPD) Full 2.9 3.7 4.5 2.9 3.7 4.5 2.9 3.7 4.5 ns

2 DCO Propagation Delay (tDCO) Full 3.9 3.9 3.9 ns

DCO to Data Skew (tSKEW) Full −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 ns

Full 12 12 12 Cycles CMOS Mode Pipeline Delay

(Latency)

12/12.5 12/12.5 12/12.5 Cycles LVDS Mode Pipeline Delay (Latency) Full

Channel A/Channel B Wake-Up Time3 Full 500 500 500 μs Out-of-Range Recovery Time Full 2 2 2 Cycles Conversion rate is the clock rate after the divider.

Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17). 3

Wake-up time is defined as the time required to return to normal operation from power-down mode.

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AD9268

TIMING SPECIFICATIONS

Table 5.

Parameter

SYNC TIMING REQUIREMENTS tSSYNC tHSYNC

SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO

Conditions

SYNC to rising edge of CLK+ setup time SYNC to rising edge of CLK+ hold time

Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK

Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge

Limit

0.3 ns typ 0.40 ns typ

2 ns min 2 ns min 40 ns min 2 ns min 2 ns min 10 ns min 10 ns min 10 ns min 10 ns min

Timing Diagrams

N – 1NVINN + 1N + 2tAN + 3N + 4N + 5tCHCLK+CLK–tCLKtDCODCOA/DCOBtSKEW08123-002CHA/CH B DATAN – 13N – 12N –11N – 10N – 9N – 8tPD

Figure 2. CMOS Default Output Mode Data Output Timing

N – 1NVINN + 1N + 2tAN + 3N + 4N + 5tCHCLK+CLK–tCLKtDCODCOA/DCOBtSKEWtPDCHA/CH B DATACH ACH BCH AN – 12N – 12N –11CH BCH ACH BN –11N – 10N – 10CH AN – 9CH BN – 9CH AN – 808123-057

Figure 3. CMOS Interleaved Output Mode Data Output Timing

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N – 1NVINN + 1N + 2AD9268tAN + 3N + 4N + 5tCHCLK+CLK–tCLKtDCODCOA/DCOBtSKEWCHA/CH B DATACH ACH BCH AN – 12N – 12N –11CH BCH ACH BN –11N – 10N – 10CH AN – 9CH BN – 9CH AN – 808123-003tPD Figure 4. LVDS Mode Data Output Timing

CLK+tSSYNCSYNCtHSYNC08123-004

Figure 5. SYNC Input Timing Requirements

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AD9268

THERMAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Table 6.

The exposed paddle must be soldered to the ground plane for Parameter Rating the LFCSP package. Soldering the exposed paddle to the PCB ELECTRICAL1

increases the reliability of the solder joints and maximizes the AVDD to AGND −0.3 V to +2.0 V

thermal capability of the package. DRVDD to AGND −0.3 V to +2.0 V

VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V Typical θJA is specified for a 4-layer PCB with a solid ground CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V plane. As shown in Table 7, airflow improves heat dissipation, SYNC to AGND −0.3 V to AVDD + 0.2 V which reduces θJA. In addition, metal in direct contact with the VREF to AGND −0.3 V to AVDD + 0.2 V package leads from metal traces, through holes, ground, and SENSE to AGND −0.3 V to AVDD + 0.2 V power planes, reduces θJA. VCM to AGND −0.3 V to AVDD + 0.2 V

Table 7. Thermal Resistance RBIAS to AGND −0.3 V to AVDD + 0.2 V

Airflow CSB to AGND −0.3 V to DRVDD + 0.2 V

Velocity SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V

Package Type (m/sec) θJA1, 2 θJC1, 3 θJB1, 4 Unit

SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V

0 18.5 1.0 °C/W 64-Lead LFCSP OEB −0.3 V to DRVDD + 0.2 V

(CP-64-6) 1.0 16.1 9.2 °C/W PDWN −0.3 V to DRVDD + 0.2 V

2.5 14.5 °C/W −0.3 V to DRVDD + 0.2 V D0A/D0B through D15A/D15B to

1AGND Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). DCOA/DCOB to AGND −0.3 V to DRVDD + 0.2 V 3

Per MIL-Std 883, Method 1012.1. 4 ENVIRONMENTAL Per JEDEC JESD51-8 (still air).

−40°C to +85°C Operating Temperature Range

(Ambient)

ESD CAUTION 150°C Maximum Junction Temperature

Under Bias

−65°C to +150°C Storage Temperature Range

(Ambient)

The inputs and outputs are rated to the supply voltage (AVDD or ARVDD) + 0.2 V but should not exceed 2.1 V.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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AD9268

AVDDAVDDVIN+BVIN–BAVDDAVDDRBIASVCMSENSEVREFAVDDAVDDVIN–AVIN+AAVDDAVDD64636261605958575655545352515049PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CLK+CLK–SYNCD0B (LSB)D1BD2BD3BD4BD5BDRVDDD6BD7BD8BD9BD10BD11B12345678910111213141516PIN 1INDICATORAD9268PARALLEL CMOSTOP VIEW(Not to Scale)48474645444342414039383736353433PDWNOEBCSBSCLK/DFSSDIO/DCSORAD15A (MSB)D14AD13AD12AD11ADRVDDD10AD9AD8AD7ANOTES1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.D12BD13BDRVDDD14BD15B (MSB)ORBDCOBDCOAD0A (LSB)D1AD2ADRVDDD3AD4AD5AD6A1718192021222324252627282930313208123-005

Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Pin No.

ADC Power Supplies 10, 19, 28, 37 49, 50, 53, 54, 59, 60, 63, 64 0

Mnemonic

DRVDD AVDD AGND,

Exposed Pad

Type

Supply Supply Ground

Description

Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal).

The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation.

ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Voltage Reference Mode Select. See Table 11 for details. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 25 D0A (LSB) Output Channel A CMOS Output Data. 26 D1A Output Channel A CMOS Output Data. 27 D2A Output Channel A CMOS Output Data. 29 D3A Output Channel A CMOS Output Data. 30 D4A Output Channel A CMOS Output Data. 31 D5A Output Channel A CMOS Output Data. 32 D6A Output Channel A CMOS Output Data.

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AD9268

Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output

Input

Input/Output Input

Input Input

Description

Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A Overrange Output. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B Overrange Output Channel A Data Clock Output. Channel B Data Clock Output.

SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low).

Output Enable Input (Active Low) in External Pin Mode.

Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.

Pin No. Mnemonic 33 D7A 34 D8A 35 D9A 36 D10A 38 D11A 39 D12A 40 D13A 41 D14A 42 D15A (MSB) 43 ORA 4 D0B (LSB) 5 D1B 6 D2B 7 D3B 8 D4B 9 D5B 11 D6B 12 D7B 13 D8B 14 D9B 15 D10B 16 D11B 17 D12B 18 D13B 20 D14B 21 D15B (MSB) 22 ORB 24 DCOA 23 DCOB SPI Control 45 SCLK/DFS 44 SDIO/DCS 46 CSB ADC Configuration 47 OEB 48 PDWN

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AVDDAVDDVIN+BVIN–BAVDDAVDDRBIASVCMSENSEVREFAVDDAVDDVIN–AVIN+AAVDDAVDD64636261605958575655545352515049AD9268

CLK+CLK–SYNCD0– (LSB)D0+ (LSB)D1–D1+D2–D2+DRVDDD3–D3+D4–D4+D5–D5+12345678910111213141516PIN 1INDICATORAD9268PARALLELLVDSTOP VIEW(Not to Scale)48474645444342414039383736353433PDWNOEBCSBSCLK/DFSSDIO/DCSOR+OR–D15+ (MSB)D15– (MSB)D14+D14–DRVDDD13+D13–D12+D12–NOTES1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.D6–D6+DRVDDD7–D7+D8–D8+DCO–DCO+D9–D9+DRVDDD10–D10+D11–D11+1718192021222324252627282930313208123-006

Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)

Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No.

ADC Power Supplies 10, 19, 28, 37 49, 50, 53, 54, 59, 60, 63, 64 0

Mnemonic

DRVDD AVDD AGND,

Exposed Pad

Type

Supply Supply Ground

Description

Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal).

The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation.

ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Voltage Reference Mode Select. See Table 11 for details. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 5 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 4 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 7 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 6 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 9 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 8 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 12 D3+ Output Channel A/Channel B LVDS Output Data 3—True.

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AD9268

Pin No. Mnemonic Type Description 11 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 14 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 13 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 16 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 15 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 18 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 17 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 21 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 20 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 23 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 22 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 27 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 26 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 30 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 29 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 32 D11+ Output Channel A/Channel B LVDS Output Data 11—True. 31 D11− Output Channel A/Channel B LVDS Output Data 11—Complement. 34 D12+ Output Channel A/Channel B LVDS Output Data 12—True. 33 D12− Output Channel A/Channel B LVDS Output Data 12—Complement. 36 D13+ Output Channel A/Channel B LVDS Output Data 13—True. 35 D13− Output Channel A/Channel B LVDS Output Data 13—Complement. 39 D14+ Output Channel A/Channel B LVDS Output Data 14—True. 38 D14− Output Channel A/Channel B LVDS Output Data 14—Complement. 41 D15+ (MSB) Output Channel A/Channel B LVDS Output Data 15—True. 40 D15− (MSB) Output Channel A/Channel B LVDS Output Data 15—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low) in External Pin Mode. 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be

configured as power-down or standby.

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AD9268

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, and 32k sample, TA = 25°C, unless otherwise noted.

0–20–40AMPLITUDE (dBFS)080MSPS2.4MHz @ –1dBFSSNR = 79.0dB (80.0dBFS)SFDR = 98dBcAMPLITUDE (dBFS)–20–40–6080MSPS200.3MHz @ –1dBFSSNR = 74.3dB (75.3dBFS)SFDR = 83dBc–60SECOND HARMONICTHIRD HARMONICSECOND HARMONICTHIRD HARMONIC–80–100–120–140010–80–100–120–14001008123-06220FREQUENCY (MHz)304020FREQUENCY (MHz)3040Figure 8. AD9268-80 Single-Tone FFT with fIN = 2.4 MHz

0–20–40AMPLITUDE (dBFS)Figure 11. AD9268-80 Single-Tone FFT with fIN = 200.1 MHz

080MSPS70.1MHz @ –6dBFSSNR = 73.0dB (79.0dBFS)SFDR = 98dBc80MSPS70.1MHz @ –1dBFSSNR = 77.5dB (78.5dBFS)SFDR = 89.2dBcAMPLITUDE (dBFS)–20–40–60–60THIRD HARMONIC–80–100–120–14001020FREQUENCY (MHz)3040SECOND HARMONICTHIRD HARMONIC–80SECOND HARMONIC–100–120–14001020FREQUENCY (MHz)304008123-063Figure 9. AD9268-80 Single-Tone FFT with fIN = 70.1 MHz

0–20–40AMPLITUDE (dBFS)Figure 12. AD9268-80 Single-Tone FFT with fIN = 70.1 MHz with Dither

Enabled

12080MSPS140.1MHz @ –1dBFSSNR = 76.0dB (77.0dBFS)SFDR = 81.1dBcSNR/SFDR (dBc AND dBFS)10080–60SECOND HARMONIC–80–100–120–140010THIRD HARMONIC6040SNR (dBFS)SFDR (dBc)SNR (dBc)SFDR (dBFS)–90–80–70–60–50–40–30INPUT AMPLITUDE (dBFS)–20–10008123-0672020FREQUENCY (MHz)3040Figure 10. AD9268-80 Single-Tone FFT with fIN = 140.1 MHz

08123-0640–100Figure 13. AD9268-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)

with fIN = 98.12 MHz

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08123-06608123-065AD9268

120200,0002.17 LSB rms180,000

110SNR/SFDR (dBFS)160,000140,000100SNRFS (DITHER ON)SNRFS (DITHER OFF)SFDRFS (DITHER ON)SFDRFS (DITHER OFF)NUMBER OF HITS120,000100,00080,00060,00040,00020,0009080N – 11N – 10N – 9N – 8N – 7N –6N – 5N – 4N – 3N – 2N – 1NN + 1N + 2N + 3N + 4N + 5N + 6N + 7N + 8N + 9N + 10N + 11OUTPUT CODE

Figure 14. AD9268-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with

fIN = 30 MHz with and without Dither Enabled

10095908580757065050100150200INPUT FREQUENCY (MHz)250300–404Figure 17. AD9268-80 Grounded Input Histogram

SNR/SFDR (dBFS/dBc)SNR @ –40°CSFDR @ –40°CSNR @ +25°CSFDR @ +25°CSNR @ +85°CSFDR @ +85°CINL ERROR (LSB)DITHER ENABLEDDITHER DISABLED20–210,00020,000

30,00040,000OUTPUT CODE50,00060,00008123-07208123-069

Figure 15. AD9268-80 Single-Tone SNR/SFDR vs. Input Frequency (fIN)

with 2 V p-p Full Scale

105SNR, CHANNEL BSFDR, CHANNEL BSNR, CHANNEL ASFDR, CHANNEL A1.000.750.50Figure 18. AD9268-80 INL with fIN = 9.7 MHz

100SNR/SFDR (dBFS AND dBc)DNL ERROR (LSB)950.250–0.25–0.50908580–0.7508123-07008123-0737525–1.00010,00020,00030,00040,000OUTPUT CODE50,00060,0003035404550556065SAMPLE RATE (MSPS)707580Figure 16. AD9268-80 Single-Tone SNR/SFDR vs. Sample Rate (fS)

with fIN = 70.1 MHz

Figure 19. AD9268-80 DNL with fIN = 9.7 MHz

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08123-071–90–80

–70–60–50–40–30INPUT AMPLITUDE (dBFS)

–20–100

08123-06870–100

0–20–40105MSPS2.4MHz @ –6dBFSSNR = 78.2dB (79.2dBFS)SFDR = 90dBc0–20–40AD9268

105MSPS200.3MHz @ –1dBFSSNR = 74.0dB (75.0dBFS)SFDR = 79dBcAMPLITUDE (dBFS)AMPLITUDE (dBFS)–60SECOND HARMONICTHIRD HARMONIC–60SECONDHARMONICTHIRD HARMONIC–80–100–120–1400102030FREQUENCY (MHz)4050–80–100–120–1400102030FREQUENCY (MHz)405008123-074Figure 20. AD9268-105 Single-Tone FFT with fIN = 2.4 MHz

0–20–40105MSPS70.1MHz @ –1dBFSSNR = 77.5dB (78.5dBFS)SFDR = 93.0dBcFigure 23. AD9268-105 Single-Tone FFT with fIN = 200.3 MHz

0–20–40105MSPS70.1MHz @ –6dBFSSNR = 72.7dB (78.7dBFS)SFDR = 97.6dBcAMPLITUDE (dBFS)–60THIRD HARMONIC–80–100–120–1400102030FREQUENCY (MHz)AMPLITUDE (dBFS)SECONDHARMONIC–60THIRD HARMONIC–80–100–120–1400102030FREQUENCY (MHz)SECONDHARMONIC08123-07540504050Figure 21. AD9268-105 Single-Tone FFT with fIN = 70.1 MHz

0–20–40Figure 24. AD9268-105 Single-Tone FFT with fIN = 70.1 MHz with Dither

Enabled

120105MSPS140.1MHz @ –1dBFSSNR = 75.7dB (76.7dBFS)SFDR = 85.5dBc100SNR/SFDR (dBc AND dBFS)AMPLITUDE (dBFS)80SECOND HARMONIC–60THIRD HARMONIC–80–100–120–1400102030FREQUENCY (MHz)40506040SNR (dBFS)SFDR (dBc)SNR (dBc)SFDR (dBFS)–90–80–70–60–50–40–30INPUT AMPLITUDE (dBFS)–20–10008123-0792008123-0760–100Figure 22. AD9268-105 Single-Tone FFT with fIN = 140.1 MHz

Figure 25. AD9268-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)

with fIN = 98.12 MHz

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08123-07808123-077AD9268

120250,0002.23 LSB rms

110SNR/SFDR (dBFS)200,000100SNRFS (DITHER ON)SNRFS (DITHER OFF)SFDRFS (DITHER ON)SFDRFS (DITHER OFF)NUMBER OF HITS150,00090100,0008050,000N – 11N – 10N – 9N – 8N – 7N – 6N – 5N – 4N – 3N – 2N – 1NN + 1N + 2N + 3N + 4N + 5N + 6N + 7N + 8N + 9N + 10N + 11OUTPUT CODE

Figure 26. AD9268-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)

with fIN = 30 MHz with and without Dither Enabled

10095SNR @ –40°CSFDR @ –40°CSNR @ +25°CSFDR @ +25°CSNR @ +85°CSFDR @ +85°CFigure 29. AD9268-105 Grounded Input Histogram

6DITHER ENABLEDDITHER DISABLED4SNR/SFDR (dBFS AND dBc)908580757065050100150200INPUT FREQUENCY (MHz)INL ERROR (LSB)20–2–408123-081250300010,00020,00030,00040,000OUTPUT CODE50,00060,000Figure 27. AD9268-105 Single-Tone SNR/SFDR vs. Input Frequency (fIN)

with 2 V p-p Full Scale

105SNR, CHANNEL BSFDR, CHANNEL BSNR, CHANNEL ASFDR, CHANNEL AFigure 30. AD9268-105 INL with fIN = 9.7 MHz

1.000.750.50100SNR/SFDR (dBFS AND dBc)DNL ERROR (LSB)950.250–0.25–0.50908580–0.7508123-082010,00020,00030,00040,000OUTPUT CODE50,00060,000Figure 28. AD9268-105 Single-Tone SNR/SFDR vs. Sample Rate (fS)

with fIN = 70.1 MHz

Figure 31. AD9268-105 DNL with fIN = 9.7 MHz

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08123-07375253035404550556065707580859095100105SAMPLE RATE (MSPS)–1.0008123-084–608123-083–90–80

–70–60–50–40–30INPUT AMPLITUDE (dBFS)

–20–100

08123-08070–100

0–20–40AMPLITUDE (dBFS)–60–80–100–120–1400

3040

FREQUENCY (MHz)

AMPLITUDE (dBFS)125MSPS2.4MHz @ –1dBFSSNR = 77.7dB (78.7dBFS)SFDR = 90dBc0–20–40–60AD9268

125MSPS140.1MHz @ –1dBFSSNR = 76.0dB (77.0dBFS)SFDR = 84.0dBcSECOND HARMONICTHIRD HARMONICTHIRD HARMONIC–80–100–120–1400

SECOND HARMONIC08123-016

03040

FREQUENCY (MHz)

5060

Figure 32. AD9268-125 Single-Tone FFT with fIN = 2.4 MHz

0–20–40125MSPS30.3MHz @ –1dBFSSNR = 77.4dB (78.4dBFS)SFDR = 91.2dBcAMPLITUDE (dBFS)Figure 35. AD9268-125 Single-Tone FFT with fIN = 140.1 MHz

125MSPS200.3MHz @ –1dBFSSNR = 74.7dB (75.7dBFS)SFDR = 80dBc–20–40–60AMPLITUDE (dBFS)–60–80–100–120–140010203040FREQUENCY (MHz)5060THIRD HARMONICSECOND HARMONICTHIRD HARMONIC–80–100–120–140SECOND HARMONIC08123-017010203040FREQUENCY (MHz)5060Figure 33. AD9268-125 Single-Tone FFT with fIN = 30.3 MHz

0–20–40125MSPS70.1MHz @ –1dBFSSNR = 77.2dB (78.2dBFS)SFDR = 87.8dBcAMPLITUDE (dBFS)Figure 36. AD9268-125 Single-Tone FFT with fIN = 200.3 MHz

0–20–40THIRD HARMONIC–60–80–100–120–140SECOND HARMONIC125MSPS220.1MHz @ –1dBFSSNR = 74.3dB (75.3dBFS)SFDR = 78.5dBcAMPLITUDE (dBFS)–60–80–100–120–14001020SECOND HARMONICTHIRD HARMONIC3040FREQUENCY (MHz)506008123-01801020

3040

FREQUENCY (MHz)

5060

08123-02108123-02008123-019

Figure 34. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz

Figure 37. AD9268-125 Single-Tone FFT with fIN = 220.1 MHz

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AD9268

0–20–40AMPLITUDE (dBFS)–60–80SECOND HARMONIC–100–120–140

3040

FREQUENCY (MHz)

THIRD HARMONIC125MSPS70.1MHz @ –6dBFSSNR = 72.2dB (78.2dBFS)SFDR = 97dBc120SFDR (dBFS)100

SNR/SFDR (dBc AND dBFS)80SNR (dBFS)60SFDR (dBc)40SNR (dBc)2008123-022–90–80

–70–60–50–40–30INPUT AMPLITUDE (dBFS)–20–10008123-02308123-0610–100

Figure 38. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −6 dBFS

with Dither Enabled

0–15–30125MSPS70.1MHz @ –23dBFSSNR = 56.8dB (79.8dBFS)SFDR = 67.7dBcFigure 41. AD9268-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)

with fIN = 2.4 MHz

120SFDR (dBFS)100SNR/SFDR (dBc AND dBFS)AMPLITUDE (dBFS)–45–60–75–90–105–120–13508123-08880SNR (dBFS)THIRD HARMONICSECOND HARMONIC60SFDR (dBc)40SNR (dBc)2006121824303642FREQUENCY (MHz)485460–90–80–70–60–50–40–30INPUT AMPLITUDE (dBFS)–20–100Figure 39. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −23 dBFS

with Dither Disabled, 1M Sample

0–15–30125MSPS70.1MHz @ –23dBFSSNR = 56.2dB (57.2dBFS)SFDR = 86.6dBcFigure 42. AD9268-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)

with fIN = 98.12 MHz

120

SFDR (DITHER ON)110SNR/SFDR (dBFS)AMPLITUDE (dBFS)–45–60–75–90–105–120–13508123-089100

SECOND HARMONICTHIRD HARMONICSFDR (DITHER OFF)90

SNR (DITHER OFF)SNR (DITHER ON)–15006121824303642FREQUENCY (MHz)48546070–100

–90–80

–70–60–50–40–30INPUT AMPLITUDE (dBFS)

–20–100

Figure 40. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −23 dBFS

with Dither Enabled, 1M Sample

Figure 43. AD9268-125 Single Tone SNR/SFDR vs. Input Amplitude (AIN)

with fIN = 30 MHz with and without Dither Enabled

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08123-024–1500–100

10095SNR @ –40°CSFDR @ –40°CSNR @ +25°CSFDR @ +25°CSNR @ +85°CSFDR @ +85°C0AD9268

–20SFDR/IMD3 (dBc AND dBFS)SNR/SFDR (dBFS AND dBc)9085SFDR (dBc)–40–60IMD3 (dBc)–80SFDR (dBFS)IMD3 (dBFS)80757065050100150200INPUT FREQUENCY (MHz)250300–10008123-025–78

–66–54–42–30INPUT AMPLITUDE (dBFS)–18–608123-02808123-02908123-030–120–90

Figure 44. AD9268-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN)

with 2 V p-p Full Scale

95908580SFDR (dBc)Figure 47. AD9268-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)

with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 125 MSPS

0–20–40125MSPS29.1MHz @ –7dBFS32.1MHz @ –7dBFSSFDR = 89dBc (96dBFS)SNR/SFDR (dBFS/dBc)AMPLITUDE (dBFS)08123-026–60–80–100–120–1400102075706560050SNR (dBFS)100150200INPUT FREQUENCY (MHz)250300

3040FREQUENCY (MHz)5060

Figure 45. AD9268-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN)

with 1 V p-p Full Scale

0Figure 48. AD9268-125 Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz

0–20125MSPS169.1MHz @ –7dBFS172.1MHz @ –7dBFSSFDR = 81.8dBc (88.8dBFS)–20SFDR/IMD3 (dBc AND dBFS)SFDR (dBc)–40IMD3 (dBc)–60–40AMPLITUDE (dBFS)08123-027–60–80–100–120–14001020–80–100SFDR (dBFS)IMD3 (dBFS)–120–90–78–66–54–42–30INPUT AMPLITUDE (dBFS)–18–6

3040FREQUENCY (MHz)5060

Figure 46. AD9268-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)

with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 125 MSPS Figure 49. AD9268-125 Two-Tone FFT with fIN1 = 169.1 MHz and

fIN2 = 172.1 MHz

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AD9268

100SFDR (dBc), CHANNEL B951.000.750.50

SNR/SFDR (dBFS/dBc)DNL ERROR (LSB)900.250–0.25–0.50–0.7585SFDR (dBc), CHANNEL ASNR (dBFS), CHANNEL B8008123-031105115125016,38432,768OUTPUT CODE49,15265,536Figure 50. AD9268-125 Single-Tone SNR/SFDR vs. Sample Rate (fS)

with fIN = 70.1 MHz

35002.27LSB rms30002500NUMBER OF HITSFigure 53. AD9268-125 DNL with fIN = 9.7 MHz

100SFDR (dBc)9080SNR (dBFS)702000150010005000SNR/SFDR (dBFS/dBc)605040300.75N – 10N – 9N – 8N – 7N – 6N – 5N – 4N – 3N – 2N – 1NN + 1N + 2N + 3N + 4N + 5N + 6N + 7N + 8N + 9N + 1008123-0590.800.850.900.951.001.051.10INPUT COMMON-MODE VOLTAGE (V)1.151.2008123-053

OUTPUT CODE

Figure 54. SNR/SFDR vs. Input Common Mode (VCM)

with fIN = 30 MHz

Figure 51. AD9268-125 Grounded Input Histogram

4DITHER ENABLEDDITHER DISABLED

2INL ERROR (LSB)0–2016,38432,768OUTPUT CODE49,15265,536Figure 52. AD9268-125 INL with fIN = 9.7 MHz

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08123-033SNR (dBFS), CHANNEL A752535455565758595SAMPLE RATE (MSPS)–1.00

AD9268

EQUIVALENT CIRCUITS

AVDDVINSENSE350Ω08123-007

Figure 55. Equivalent Analog Input Circuit

AVDDFigure 60. Equivalent SENSE Circuit

DRVDD0.9VCLK+10kΩ10kΩCLK–CSB350Ω26kΩ08123-01208123-008Figure 56. Equivalent Clock Input Circuit Figure 61. Equivalent CSB Input Circuit

DRVDDAVDDPADVREF6kΩ08123-009

Figure 62. Equivalent VREF Circuit

Figure 57. Digital Output

DRVDD26kΩSDIO/DCS350ΩPDWN350Ω26kΩ08123-01408123-01008123-01508123-013

Figure 63. Equivalent PDWN Input Circuit

Figure 58. Equivalent SDIO/DCS Circuit

DRVDDSCLK/DFSOR OEB350Ω26kΩ08123-011Figure 59. Equivalent SCLK/DFS or OEB Input Circuit

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AD9268

A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application.

In intermediate frequency (IF) undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, “Transformer-Coupled Front-End for Wideband A/D Converters,” for more information on this subject (refer to www.analog.com).

BIASSCSVIN+CPAR1CPAR2HCSVIN–S08123-034THEORY OF OPERATION

The AD9268 dual-core analog-to-digital converter (ADC) design can be used for diversity reception of signals, in which the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with inde-pendent analog inputs. The user can sample any fS/2 frequency segment from dc to 200 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 300 MHz analog input is permitted, but it occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD9268 can be used as a base-band or direct downconversion receiver, in which one ADC is used for I input data, and the other is used for Q input data. Synchronization capability is provided to allow synchronized timing between multiple devices.

Programming and control of the AD9268 are accomplished using a 3-wire SPI-compatible serial interface.

SCFBADC ARCHITECTURE

The AD9268 architecture consists of a dual front-end sample-and-hold circuit, followed by a pipelined, switched-capacitor ADC. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digital-to-analog converter (DAC) and an interstage residue amplifier (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.

The input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. During power-down, the output buffers go into a high impedance state.

SSCPAR1CPAR2BIASSCFB

Figure 64. Switched-Capacitor Input

For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched, and the inputs should be differentially balanced.

An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core. The span of the ADC core is set by this buffer to 2 × VREF.

Input Common Mode

The analog inputs of the AD9268 are not internally dc biased. In ac-coupled applications, the user must provide this bias exter-nally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 54). An on-board common-mode voltage reference is included in the design and is available from the VCM pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9268 is a differential switched-capacitor circuit that has been designed for optimum performance while processing a differential input signal.

The clock signal alternatively switches the input between sample mode and hold mode (see Figure 64). When the input is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within ½ of a clock cycle.

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AD9268

typically at very low levels and do not limit SFDR when the ADC is quantizing large-signal inputs, dithering converts these tones to noise and produces a whiter noise floor. Small-Signal FFT

For small-signal inputs, the front-end sampling circuit typically contributes very little distortion, and, therefore, the SFDR is likely to be limited by tones caused by DNL errors due to random com-ponent mismatches. Therefore, for small-signal inputs (typically, those below −6 dBFS), dithering can significantly improve SFDR by converting these DNL tones to white noise. Static Linearity

Dithering also removes sharp local discontinuities in the INL transfer function of the ADC and reduces the overall peak-to-peak INL.

In receiver applications, utilizing dither helps to reduce DNL errors that cause small-signal gain errors. Often this issue is overcome by setting the input noise 5 dB to 10 dB above the converter noise. By utilizing dither within the converter to correct the DNL errors, the input noise requirement can be reduced.

Common-Mode Voltage Servo

In applications where there may be a voltage loss between the VCM output of the AD9268 and the analog inputs, the common-mode voltage servo can be enabled. When the inputs are ac-coupled and a resistance of >100 Ω is placed between the VCM output and the analog inputs, a significant voltage drop can occur and the common-mode voltage servo should be enabled. Setting Bit 0 in Register 0x0F to a logic high enables the VCM servo mode. In this mode, the AD9268 monitors the common-mode input level at the analog inputs and adjusts the VCM output level to keep the common-mode input voltage at an optimal level. If both channels are operational, Channel A is monitored. However, if Channel A is in power-down or standby mode, then the Channel B input is monitored.

Dither

The AD9268 has an optional dither mode that can be selected for one or both channels. Dithering is the act of injecting a known but random amount of white noise, commonly referred to as dither, into the input of the ADC. Dithering has the effect of improving the local linearity at various points along the ADC transfer function. Dithering can significantly improve the SFDR when quantizing small-signal inputs, typically when the input level is below −6 dBFS.

As shown in Figure 65, the dither that is added to the input of the ADC through the dither DAC is precisely subtracted out digitally to minimize SNR degradation. When dithering is enabled, the dither DAC is driven by a pseudorandom number generator (PN gen). In the AD9268, the dither DAC is precisely calibrated to result in only a very small degradation in SNR and SINAD. The typical SNR and SINAD degradation values, with dithering enabled, are only 1 dB and 0.8 dB, respectively.

AD9268VINADC COREDOUTDifferential Input Configurations

Optimum performance is achieved while driving the AD9268 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC.

The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9268 (see Figure 66), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

15pF200ΩVIN76.8Ω90Ω33Ω5pF15ΩVIN–AVDDADA4938-2DITHERDAC0.1µF120Ω15pF200Ω33Ω15ΩAD9268VIN+VCM08123-035PN GENDITHER ENABLE08123-058

Figure 66. Differential Input Configuration Using the ADA4938-2

Figure 65. Dither Block Diagram

Large-Signal FFT

In most cases, dithering does not improve SFDR for large-signal inputs close to full scale, for example, with a −1 dBFS input. For large-signal inputs, the SFDR is typically limited by front-end sampling distortion, which dithering cannot improve. However, even for such large-signal inputs, dithering may be useful for certain applications because it makes the noise floor whiter. As is common in pipeline ADCs, the AD9268 contains small DNL errors caused by random component mismatches that produce spurs or tones that make the noise floor somewhat randomly colored part-to-part. Although these tones are

For baseband applications in which SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 67. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer.

C2R2R12V p-p49.9ΩC1R1R2VIN+AD9268VIN–VCM08123-0360.1µFC2

Figure 67. Differential Transformer-Coupled Configuration

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AD9268

achieved by using a ferrite bead in series with a resistor and removing the capacitors. However, these values are dependent on the input signal and should be used only as a starting guide. Table 10. Example RC Network

Frequency Range (MHz) 0 to 100 100 to 200 100 to 300

The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion.

At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9268. For applications in which SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 68). In this configuration, the input is ac-coupled, and the CML is provided to each input through a 33 Ω resistor. These resistors compensate for losses in the input baluns to provide a 50 Ω impedance to the driver.

In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input fre-quency and source impedance and may need to be reduced or removed. Table 10 displays recommended values to set the RC network. At higher input frequencies, good performance can be 0.1µF2V p-pPASSP0.1µF33Ω0.1µF33ΩR1 SeriesC1 Differential R2 Series (Ω Each) (pF) (Ω Each) 33 5 15 10 5 10 1

10 Remove 66 C2 Shunt (pF Each) 15 10

Remove

In this configuration, R1 is a ferrite bead with a value of 10 Ω @ 100 MHz.

An alternative to using a transformer-coupled input at fre-quencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 69. See the AD8352 data sheet for more information.

C2R1R2VIN+0.1µFC1R1R2AD9268VIN–VCM08123-038C2

Figure 68. Differential Double Balun Input Configuration

VCC0.1µFANALOG INPUT0Ω1612CDRDRG34ANALOG INPUT0.1µF50Ω140.1µF0.1µF8, 13110.1µF0.1µFR200ΩVIN+C0.1µF200ΩRAD835210AD9268VIN–VCM08123-039

Figure 69. Differential Input Configuration Using the AD8352

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AD9268

If a resistor divider is connected external to the chip, as shown in Figure 71, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output, defined as follows:

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9268. The input range can be adjusted by varying the reference voltage applied to the AD9268, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference.

R2⎞

VREF=0.5×⎛⎜1+⎟

R1⎠⎝

The input range of the ADC always equals twice the voltage at

the reference pin (VREF) for either an internal or an external reference.

VIN+A/VIN+BVIN–A/VIN–BInternal Reference Connection

A comparator within the AD9268 detects the potential at the SENSE pin and configures the reference into four possible modes, which are summarized in Table 11. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 70), setting VREF to 1.0 V for a 2.0 V p-p full-scale input. In this mode, with SENSE grounded, the full scale can also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of Register 0x18. These bits can be used to change the full scale to 1.25 V p-p, 1.5 V p-p, 1.75 V p-p, or to the default of 2.0 V p-p, as shown in Table 17.

Connecting the SENSE pin to the VREF pin switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output for a 1 V p-p full-scale input.

VIN+A/VIN+BVIN–A/VIN–BADCCOREVREF1.0µF0.1µFR2SENSESELECTLOGICR10.5V08123-041AD9268Figure 71. Programmable Reference Configuration

ADCCOREIf the internal reference of the AD9268 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 72 shows how the internal reference voltage is affected by loading.

0VREF1.0µF0.1µFREFERENCE VOLTAGE ERROR (%)–0.5VREF = 0.5V–1.0VREF = 1V–1.5SELECTLOGICSENSE0.5V08123-040AD9268Figure 70. Internal Reference Configuration

–2.0–2.50.40.60.81.01.21.4LOAD CURRENT (mA)1.61.82.008123-054–3.00.2

Figure 72. Reference Voltage Accuracy vs. Load Current

Table 11. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V Resulting VREF (V) N/A 0.5 Resulting Differential Span (V p-p) 2 × external reference 1.0 2 × VREF 2.0 R2⎞⎛0.5×⎜1+⎟ (see Figure 71) R1⎝⎠1.0 Rev. A | Page 29 of 44

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AD9268

The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recom-mended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9268 to approx-imately 0.8 V p-p differential.

This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9268 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance.

Mini-Circuits®ADT1-1WT, 1:1Z0.1µFXFMR100Ω0.1µFCLK–0.1µF08123-045External Reference Operation

The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac-teristics. Figure 73 shows the typical drift characteristics of the internal reference in 1.0 V mode.

When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 6 kΩ load (see Figure 62). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V.

2.01.5VREF = 1.0V1.00.50–0.5–1.0–1.508123-055ADCREFERENCE VOLTAGE ERROR (mV)CLOCKINPUT0.1µF50ΩAD9268CLK+SCHOTTKYDIODES:HSMS2822

Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz)

ADCCLOCKINPUT1nF50Ω1nF0.1µFAD9268CLK+–2.0–400.1µFCLK–SCHOTTKYDIODES:HSMS282208123-046–2002040TEMPERATURE (°C)6080

Figure 73. Typical VREF Drift

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9268 sample clock inputs, CLK+ and CLK−, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 74) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking.

AVDDCLOCKINPUTFigure 76. Balun-Coupled Differential Clock (Up to 625 MHz)

If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 77. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock drivers offer excellent jitter performance.

0.1µF0.1µFCLK+0.9VCLK+4pF4pF08123-044AD951x0.1µFPECL DRIVER240Ω240Ω100Ω0.1µFADCAD9268CLK–08123-047CLK–CLOCKINPUT50kΩ50kΩ

Figure 77. Differential PECL Sample Clock (Up to 625 MHz)

Figure 74. Equivalent Clock Input Circuit

Clock Input Options

The AD9268 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 75 and Figure 76 show two preferred methods for clocking the AD9268 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer.

A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 78. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/ AD9518 clock drivers offer excellent jitter performance.

0.1µFCLOCKINPUT0.1µFCLK+AD951x0.1µFCLOCKINPUT50kΩ50kΩLVDS DRIVER100Ω0.1µFADCAD9268CLK–08123-048

Figure 78. Differential LVDS Sample Clock (Up to 625 MHz)

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AD9268

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the clock input. For inputs near full scale, the degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by

SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10(−SNRLF/10)]

AD951xCMOS DRIVER50Ω11kΩOPTIONAL0.1µF100ΩCLK+In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended CMOS signal. In such applica-tions, the CLK+ pin should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor (see Figure 79).

VCC0.1µFCLOCKINPUT1kΩADCAD9268CLK–0.1µF08123-049150Ω RESISTOR IS OPTIONAL.

In the equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 80. The measured curve in Figure 80 was taken using an ADC clock source with approxi-mately 65 fs of jitter, which combines with the 70 fs of jitter inherent in the AD9268 to produce the results shown.

800.05psMEASURED70Figure 79. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9268 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. For divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS) is optional. For other divide ratios, divide by 3, 5, 6, 7, and 8, the duty cycle stabilizer must be enabled for proper part operation. The AD9268 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchro-nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling.

75SNR (dBc)0.20ps65600.50ps551.00ps1.50ps110100INPUT FREQUENCY (MHz)1k08123-05050

Figure 80. SNR vs. Input Frequency and Jitter

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. The AD9268 requires a tight tolerance on the clock duty cycle to maintain dynamic performance characteristics.

The AD9268 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the perfor-mance of the AD9268. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS enabled.

Jitter in the rising edge of the input is still of paramount concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance.

The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9268. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step.

Refer to the AN-501 Application Note and the AN-756 Application Note (see www.analog.com) for more information about jitter performance as it relates to ADCs.

CHANNEL/CHIP SYNCHRONIZATION

The AD9268 has a SYNC input that offers the user flexible synchronization options for synchronizing the clock divider. The clock divider sync feature is useful for guaranteeing synchro-nized sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence.

The SYNC input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty between multiple parts, the SYNC input signal should be externally syn-chronized to the input clock signal, meeting the setup and hold times shown in Table 5. The SYNC input should be driven using a single-ended CMOS-type signal.

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1.0IAVDD0.80.200.25POWER DISSIPATION AND STANDBY MODE

As shown in Figure 81, the power dissipated by the AD9268 varies with its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit.

The maximum DRVDD current (IDRVDD) can be calculated as

IDRVDD = VDRVDD × CLOAD × fCLK × N

where N is the number of output bits (32 plus two DCO outputs, in the case of the AD9268).

This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is estab-lished by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal.

Reducing the capacitive load presented to the output drivers reduces digital power consumption. The data in Figure 81 was taken in LVDS output mode, using the same operating conditions as those used for the Typical Performance Characteristics.

1.250.50.6TOTAL POWER0.150.40.100.2IDRVDD0.0535455565ENCODE FREQUENCY (MSPS)7508123-0870250SUPPLY CURRENT (A)TOTAL POWER (W)Figure 83. AD9268-80 Power and Current vs. Encode Frequency (LVDS

Output Mode)

By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9268 is placed in power-down mode. In this state, the ADC typically dissipates 3.3 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9268 to its normal operating mode.

Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation.

When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required.

1.000.40.75TOTAL POWER0.500.30.20.25IDRVDD0.1 SUPPLY CURRENT (A)TOTAL POWER (W)IAVDDDIGITAL OUTPUTS

08123-056025

Figure 81. AD9268-125 Power and Current vs. Encode Frequency (LVDS

Output Mode)

1.00.57510050ENCODE FREQUENCY (MHz)0125The AD9268 output drivers can be configured to interface with 1.8 V CMOS logic families. The AD9268 can also be configured for LVDS outputs (standard ANSI or reduced output swing mode) using a DRVDD supply voltage of 1.8 V.

In CMOS output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. The default output mode is CMOS, with each channel output on separate busses as shown in Figure 2. The output can also be configured for interleaved CMOS via the SPI port. In interleaved CMOS mode, the data for both channels is output through the Channel A output bits, and the Channel B output is placed into high impedance mode. The timing diagram for interleaved CMOS output mode is shown in Figure 3.

The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 12).

0.8TOTAL POWER0.40.60.30.4IAVDD0.2IDRVDD0.10.2354555657585ENCODE FREQUENCY (MSPS)9508123-0860250105SUPPLY CURRENT (A)TOTAL POWER (W)

Figure 82. AD9268-105 Power and Current vs. Encode Frequency (LVDS

Output Mode)

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TIMING

The AD9268 provides latched data with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal.

The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9268. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9268 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade.

As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Table 12. SCLK/DFS Mode Selection (External Pin Mode)

Voltage at Pin SCLK/DFS SDIO/DCS AGND Offset binary (default) DCS disabled AVDD Twos complement DCS enabled

(default)

Digital Output Enable Function (OEB)

The AD9268 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OEB pin or through the SPI. If the OEB pin is low, the output data drivers and DCOs are enabled. If the OEB pin is high, the output data drivers and DCOs are placed in a high impedance state. This OEB

function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage.

When using the SPI, the data outputs and DCO of each channel can be independently three-stated by using the output enable bar bit (Bit 4) in Register 0x14. Table 13. Output Data Format

Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN−

Condition (V) < −VREF − 0.5 LSB = −VREF = 0

= +VREF − 1.0 LSB > +VREF − 0.5 LSB

Data Clock Output (DCO)

The AD9268 provides two data clock output (DCO) signals intended for capturing the data in an external register. In CMOS output mode, the data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. In LVDS output mode, the DCO and data output switching edges are closely aligned. Additional delay can be added to the DCO output using SPI Register 0x17 to increase the data setup time. In this case, the Channel A output data is valid on the rising edge of DCO, and the Channel B output data is valid on the falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for a graphical timing description of the output modes.

Twos Complement Mode 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1111

OR 1 0 0 0 1

Offset Binary Output Mode 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111

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The outputs are not disconnected during this test, so the PN sequence can be observed as it runs. The PN sequence can be continued from its last value or reset from the beginning, based on the value programmed in Register 0x0E, Bit 2. The BIST signature result varies based on the channel configuration.

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9268 includes built-in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the integrity of the digital datapath of the AD9268. Various output test options are also provided to place predictable values on the outputs of the AD9268.

OUTPUT TEST MODES

The output test options are shown in Table 17. When an output test mode is enabled, the analog section of the ADC is discon-nected from the digital back end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The seed value for the PN sequence tests can be forced if the PN reset bits are used to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected AD9268 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath starting at the ADC block output. The BIST sequence runs for 512 cycles and stops. The BIST signature value for Channel A or Channel B is placed in Register 0x24 and Register 0x25. If one channel is chosen, its BIST signature is written to the two registers. If both channels are chosen, the results from Channel A are placed in the BIST signature registers.

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AD9268

The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 84 and Table 5.

Other modes involving the CSB are available. When the CSB is held low indefinitely, which permanently enables the device, this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits.

In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame.

All data is composed of 8-bit words. Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

SERIAL PORT INTERFACE (SPI)

The AD9268 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are docu-mented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK/DFS pin, the SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO/DCS (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active-low control that enables or disables the read and write cycles. Table 14. Serial Port Interface Pins

Pin Function SCLK Serial Clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

SDIO Serial Data Input/Output. A dual-purpose pin that

typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame.

CSB Chip Select Bar. An active-low control that gates the read

and write cycles.

tDStSCSBtHIGHtDHtLOWtCLKtHSCLKDON’T CAREDON’T CARESDIODON’T CARER/WW1W0A12A11A10A9A8A7D5D4D3D2D1D0DON’T CARE08123-052

Figure 84. Serial Port Interface Timing Diagram

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AD9268

When the device is in SPI mode, the PDWN and OEB pins remain active. For SPI control of output enable and power-down, the OEB and PDWN pins should be set to their default states. Table 15. Mode Selection

External

Pin Voltage Configuration SDIO/DCS AVDD (default) Duty cycle stabilizer enabled

AGND Duty cycle stabilizer disabled

SCLK/DFS AVDD Twos complement enabled

AGND (default) Offset binary enabled

OEB AVDD Outputs in high impedance

AGND (default) Outputs enabled

PDWN AVDD Chip in power-down or

standby

AGND (default) Normal operation

HARDWARE INTERFACE

The pins described in Table 14 comprise the physical interface between the user programming device and the serial port of the AD9268. The SCLK pin and the CSB pin function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback.

The SPI is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Micro-controller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9268 to prevent these signals from transi-tioning at the converter inputs during critical sampling periods. Some pins serve a dual function when the SPI is not being used. When the pins are strapped to AVDD or ground during device power-on, they are associated with a specific function. The Digital Outputs section describes the strappable functions supported on the AD9268.

SPI ACCESSIBLE FEATURES

Table 16 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9268 part-specific features are described in detail following Table 17, the external memory map register table. Table 16. Features Accessible Using the SPI

Feature Name Mode Clock

Description

Allows the user to set either power-down mode or standby mode

Allows the user to access the DCS, set the clock divider, set the clock divider phase, and enable the sync

Allows the user to digitally adjust the converter offset

Allows the user to set test modes to have known data on output bits

Allows the user to set the output mode, including LVDS

Allows the user to set the output clock polarity Allows the user to vary the DCO delay

Allows the user to set the reference voltage

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the

PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control. In this mode, the CSB chip select bar should be connected to AVDD, which disables the serial port interface.

Offset Test I/O Output Mode Output Phase Output Delay VREF

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AD9268

Logic Levels

An explanation of logic level terminology follows: • •

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x30); and the digital feature control register (Address 0x100).

The memory map register table (see Table 17) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x18, the VREF select register, has a hexadecimal default value of 0xC0. This means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting is the default reference selection setting. The default value uses a 2.0 V p-p reference. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining register, Register 0x100, is documented in the Memory Map Register Table section.

“Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.”

“Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 through Address 0x18 and Address 0x30 are shadowed. Writes to these addresses do not affect part

operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and the bit autoclears.

Channel-Specific Registers

Some channel setup functions, such as the signal monitor

thresholds, can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 17 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 17 affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits.

Open Locations

All address and bit locations that are not included in Table 17 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written.

Default Values

After the AD9268 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 17.

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AD9268

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers

Address Register Bit 7 (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

GChip Configuration Registers 0x00 0 LSB first Soft reset 1 1 Soft reset SPI port

configuration (global)

Bit 1 LSB first

Bit 0 (LSB) 0

Default Value (Hex) 0x18

Default Notes/ Comments

0x01 Chip ID

(global)

0x02 Chip grade Open Open (global)

8-bit Chip ID[7:0] (AD9268 = 0x32)

(default)

Speed grade ID Open Open Open Open 01 = 125 MSPS 10 = 105 MSPS 11 = 80 MSPS

Data

Channel A (default)

0x03

The nibbles are mirrored so LSB-first mode or MSB-first mode registers correctly, regardless of shift mode

0x32 Read only

Speed grade

ID used to differentiate devices; read only

Channel Index and Transfer Registers 0x05 Open Open Open Open Open Open Data Channel

index Channel

(default)

Bits are set to determine which device on the chip receives the next write command; applies to local registers only

0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously

transfers data from the master shift register to the slave

ADC Functions

0x08 Power modes 1 Open Open Open Open Internal power-down 0x80 External Determines

power-mode (local) various generic (local)

down pin modes of chip 00 = normal operation function operation 01 = full power-down (local) 10 = standby 0 = pdwn 11 = normal operation 1 = stndby

0x09 lobal clock Open Open Open Open Open Open Open Duty cycle 0x01 stabilizer (global)

(default)

0x0B Clock divide Open Open Open Open Open Clock divide ratio 0x00 Clock divide

values other (global) 000 = divide by 1

than 000 001 = divide by 2

automatically 010 = divide by 3

cause the duty

011 = divide by 4

cycle stabilizer

100 = divide by 5 to become 101 = divide by 6 active 110 = divide by 7 111 = divide by 8

0x0D Open Open Reset PN Open Output test mode 0x00 Test mode Reset When this

(local) long gen PN short register is set, 000 = off (default)

gen the test data 001 = midscale short

is placed on 010 = positive FS

the output

011 = negative FS

pins in place of

100 = alternating checkerboard normal data 101 = PN long sequence 110 = PN short sequence 111 = one/zero word toggle

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AD9268

Default Default Value Notes/ Address Register Bit 7 Bit 0

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (Hex) Name (MSB) (LSB) (Hex) Comments

0x0E BIST enable Open Open Open Open Open Reset BIST Open 0x04 BIST

sequence enable (global)

0x0F Open Open Open Open Open Open Open Common-0x00 ADC input

(global) mode

servo enable

0x10 Offset adjust 0x00 Offset adjust in LSBs from +127 to −128

(twos complement format) (local)

0x14 Output mode Output format 0x00 Drive Output CMOS Output Open Output Configures the

strength type output enable (must be invert outputs and 00 = offset binary

bar written (local) the format of 0 = ANSI 0 = CMOS interleave 01 = twos (local) low) the data LVDS; 1 = LVDS enable complement

1 = (global) (global) 01 = gray code reduced 11 = offset binary swing (local) LVDS (global)

0x16 Open Open Open Open Input clock divider phase adjust 0x00 Clock phase Invert Allows

control DCO clock selection of 000 = no delay (global) clock delays 001 = 1 input clock cycle

into the input 010 = 2 input clock cycles

clock divider

011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles

0x17 Open Open Open DCO clock delay 0x00 DCO output

delay (global) (delay = 2500 ps × register value/31)

00000 = 0 ps 00001 = 81 ps 00010 = 161 ps …

11110 = 2419 ps 11111 = 2500 ps

0x18 VREF select Open Open Open Open Open Open 0xC0 Reference voltage

selection (global)

00 = 1.25 V p-p 01 = 1.5 V p-p 10 = 1.75 V p-p 11 = 2.0 V p-p (default)

0x24 BIST signature[7:0] 0x00 Read only BIST signature

LSB (local)

0x25 BIST signature[15:8] 0x00 Read only BIST signature

MSB (local)

0x30 Open Open Open Open 0x00 Dither enable Open Open Open Dither (local) enable

Digital Feature Control 0x100 Sync control Open Open Open Open Open Clock 0x00 Clock Master

divider divider sync (global)

next sync sync enable only enable

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AD9268

ignore the rest. The clock divider sync enable bit (Address 0x100, Bit 1) resets after it syncs.

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode.

Sync Control (Register 0x100) Bits[7:3]—Reserved

Bit 2—Clock Divider Next Sync Only

If the master sync enable bit (Address 0x100, Bit 0) and the clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to

Bit 0—Master Sync Enable

Bit 0 must be high to enable any of the sync functions. If the sync capability is not used this bit should remain low to conserve power.

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AD9268

The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged to prevent solder wicking through the vias, which can compromise the connection.

To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9268 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9268, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD several different decoupling capa-citors should be used to cover both high and low frequencies. Place these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. A single PCB ground plane should be sufficient when using the AD9268. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved.

VCM

The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 67.

LVDS Operation

The AD9268 defaults to CMOS output mode on power-up. If LVDS operation is desired, this mode must be programmed, using the SPI configuration registers after power-up. When the AD9268 powers up in CMOS mode with LVDS termination resistors (100 Ω) on the outputs, the DRVDD current can be higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage to the AD9268, but it should be taken into account when consid-ering the maximum DRVDD current for the part.

To avoid this additional DRVDD current, the AD9268 outputs can be disabled at power-up by taking the OEB pin high. After the part is placed in LVDS mode via the SPI port, the OEB pin can be taken low to enable the outputs.

RBIAS

The AD9268 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance.

Reference Decoupling

The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor.

SPI Port

The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9268 to keep these signals from transitioning at the converter inputs during critical sampling periods.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9268 exposed paddle, Pin 0.

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AD9268

9.00BSCSQ0.60MAX0.60MAX48PIN1INDICATOR49641OUTLINE DIMENSIONS

PIN1

INDICATORTOPVIEW8.75BSCSQ0.50BSCEXPOSEDPAD(BOTTOMVIEW)7.657.50SQ7.350.500.400.300.80MAX0.65TYP0.05MAX0.02NOM

0.300.230.180.20REF333216171.000.850.8012°MAX7.50REF0.25MIN

SEATINGPLANEFORPROPERCONNECTIONOFTHEEXPOSEDPAD,REFERTOTHEPINCONFIGURATIONANDFUNCTIONDESCRIPTIONS

SECTIONOFTHISDATASHEET.

COMPLIANTTOJEDECSTANDARDSMO-220-VMMD-4

041509-A

Figure 85. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-6)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description AD9268BCPZ-801−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] AD9268BCPZRL7-801−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

AD9268BCPZ-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] AD9268BCPZRL7-1051−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

AD9268BCPZ-125−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

AD9268BCPZRL7-125−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] AD9268-80EBZ1 Evaluation Board

AD9268-105EBZ Evaluation Board AD9268-125EBZ1 Evaluation Board

Package Option

CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-6

Z = RoHS Compliant Part.

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