METHOD OF MANUFACTURING VERTICAL TRANSISTORS

专利名称：METHOD OF MANUFACTURING VERTICAL

TRANSISTORS

发明人：Hsiao-chia Chen,Sheng-chang Liang,Chien-hua Tsai,Masahiko Ohuchi

申请号：US13313566申请日：20111207

公开号：US20130146561A1公开日：20130613

专利附图：

摘要：A method of manufacturing vertical transistors includes steps of: forming aconductive layer on the surface of a substrate with a ditch and two support portions;

removing the conductive layer on the bottom wall of the ditch and top walls of thesupport portions via anisotropic etching through a etch back process; forming an oxidizedportion in the ditch; and etching the conductive layer to form two gates withoutcontacting each other. By forming the conductive layer on the surface of the ditch andadopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur inthe conventional etching process is prevented, and the risk of damaging metal wirescaused by increasing etching duration also can be averted.

申请人：Hsiao-chia Chen,Sheng-chang Liang,Chien-hua Tsai,Masahiko Ohuchi

地址：Taichung City TW,Taichung City TW,Taichung City TW,Taichung City TW

国籍：TW,TW,TW,TW

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