Freescale SemiconductorData Sheet:
Document Number: MSC8126
Rev. 13, 12/2007
MSC8126
Quad Digital Signal Processor
•Four StarCore™ SC140 DSP extended cores, each with an SC140 DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte total), 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, external cache support, programmable interrupt controller (PIC), local interrupt controller (LIC), and low-power Wait and Stop processing modes.
•475 Kbyte M2 memory for critical data/temporary data buffering.•4 Kbyte boot ROM.
•M2-accessible multi-core MQBus connecting the M2 memory with all four cores, operating at the core frequency, with data bus access of up to 128-bit reads and up to -bit writes, central efficient round-robin arbiter for core access to the bus, and atomic control of M2 memory access by the cores and local bus.
•Internal PLL configured are reset by configuration signal values.•60x-compatible system bus with or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of /32/16/8 bits controlled by the internal memory controller,.access to external memory or peripherals, access by an external host to internal resources, slave support with direct access to internal resources including M1 and M2 memories, and on-device arbitration for up to four master devices.
•Direct slave interface (DSI) using a 32/-bit slave interface with 21–25 bit addressing and 32/-bit data transfers, direct access by an external host to internal/external resources, synchronous or asynchronous accesses with burst capability in synchronous mode, dual or single strobe mode, write and read buffers to improve host bandwidth, byte enable signals for 1/2/4/8-byte write granularity, sliding window mode for access using a reduced number of address pins, chip ID decoding to allow one CS signal to control multiple DSPs, broadcast mode to write to multiple DSPs, and big-endian/little-endian/munged support.
•Three mode signal multiplexing: -bit DSI/32-bit system bus, 32-bit DSI/-bit system bus, or 32-bit DSI/32-bit system bus.•Flexible memory controller with three UPMs, a GPCM, a
page-mode SDRAM machine, glueless interface to a variety of memories and devices, byte enables for -/32-bit bus widths, 8 memory banks for external memories, and 2 memory banks for IPBus peripherals and internal memories.
•Multi-channel DMA controller with 16 time-multiplexed single channels, up to four external peripherals, DONE or DRACK protocol for two external peripherals,.service for up to 16 internal requests from up to 8 internal FIFOs per channel, FIFO generated watermarks and hungry requests, priority-based
time-multiplexing between channels using 16 internal priority
FC PBGA–43120mm×20mm•
•
••••••
••
•
levels or round-robin time-multiplexing between channels, flexible channel configuration with connection to local bus or system bus, and flyby transfer support that bypasses the FIFO.Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97.
Ethernet controller: support for 10/100 Mbps MII/RMII/SMII including full- and half-duplex operation, full-duplex flow controls, out-of-sequence transmit queues, programmable
maximum frame length including jumbo frames and VLAN tags and priority, retransmission after collision, CRC generation and verification of inbound/outbound packets, address recognition (including exact match, broadcast address, individual hash check, group hash check, and promiscuous mode), pattern matching, insertion with expansion or replacement for transmit frames, VLAN tag insertion, RMON statistics, local bus master DMA for descriptor fetching and buffer access, and optional multiplexing with GPIO (MII/RMII/SMII) or DSI/system bus signals lines (MII/RMII).
UART with full-duplex operation up to 6.25 Mbps.Up to 32 general-purpose input/output (GPIO) ports.I2C interface that allows booting from EEPROM devices.
Two timer modules, each with sixteen configurable 16-bit timers.Eight programmable hardware semaphores.
Global interrupt controller (GIC) with interrupt consolidation and routing to INT_OUT, NMI_OUT, and the cores; thirty-two virtual maskable interrupts (8 per core) and four virtual NMI (one per core) that can be generated by a simple write access.
Boot options: external memory, external host, UART, TDM, or I2C.
VCOP with fully programmable feed-forward channel decoding, feed-forward channel equalization and traceback sessions. Up to 400 3GPP 12.2 kbps AMR channels (channel decoding, number of channels linear to frequency). Up to 200 blind transport format detect (BTFD) channels according to the 3GPP standard. Number of channels linear to frequency.
TCOP with full support for 3GPP and CDMA2000 standards in Turbo decode; up to 20 turbo-coding 384 kbps channels; 8 state PCCC with polynomial as supported by the 3G standards; iterative decoding structure based on Maximum A-Posteriori probability (MAP), with calculations performed in the LOG domain.
©Freescale Semiconductor, Inc., 2004, 2007. All rights reserved.
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Table of Contents
12
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.1FC-PBGA Ball Layout Diagrams. . . . . . . . . . . . . . . . . . .41.2Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .7Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.1Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.2Recommended Operating Conditions. . . . . . . . . . . . . .142.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .142.4DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .152.5AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .403.1Start-up Sequencing Recommendations . . . . . . . . . . .403.2Power Supply Design Considerations. . . . . . . . . . . . . .403.3Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .423.4External SDRAM Selection. . . . . . . . . . . . . . . . . . . . . .433.5Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . .44Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure9.Timing Diagram for a Reset Configuration Write. . . . . . 21Figure10.Internal Tick Spacing for Memory Controller Signals. . . 22Figure11.SIU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure12.CLKOUT and CLKIN Signals. . . . . . . . . . . . . . . . . . . . . 26Figure13.DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure14.Asynchronous Single- and Dual-Strobe Modes Read
Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure15.Asynchronous Single- and Dual-Strobe Modes Write
Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure16.Asynchronous Broadcast Write Timing Diagram. . . . . . 30Figure17.DSI Synchronous Mode Signals Timing Diagram . . . . . 31Figure18.TDM Inputs Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure19.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure20.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure21.UART Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure22.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure23.MDIO Timing Relationship to MDC . . . . . . . . . . . . . . . . 34Figure24.MII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . 35Figure26.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 36Figure27.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure28.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure29.Test Clock Input Timing Diagram. . . . . . . . . . . . . . . . . . 38Figure30.Boundary Scan (JTAG) Timing Diagram. . . . . . . . . . . . 38Figure31.Test Access Port Timing Diagram . . . . . . . . . . . . . . . . . 39Figure32.TRST Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 39Figure33.Core Power Supply Decoupling. . . . . . . . . . . . . . . . . . . 41Figure34.VCCSYN Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure35.MSC8126 Mechanical Information, 431-pin FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3
4567
List of Figures
Figure1.Figure2.Figure3.Figure4.Figure5.Figure6.Figure7.
MSC8126 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3StarCore SC140 DSP Extended Core Block Diagram . . 3MSC8126 Package, Top View . . . . . . . . . . . . . . . . . . . . 5MSC8126 Package, Bottom View. . . . . . . . . . . . . . . . . . 6Overshoot/Undershoot Voltage for VIH and VIL. . . . . . . 16Start-Up Sequence: VDD and VDDH Raised Together. . 17Start-Up Sequence: VDD Raised Before VDDH with CLKIN Started with VDDH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure8.Power-Up Sequence for VDDH and VDD/VCCSYN . . . . . 18
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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SC140Extended CoreMQBusBootROMSC140Extended Core128SC140Extended CoreSC140Extended Core128IP MasterSQBusLocal Bus32 TimersM2RAMM2RAMMemoryControllerUART4 TDMsTCOPVCOPPLL/ClockJTAG PortIP MasterIPBus232PLLJTAGSystemInterfaceInternal Local BusSIURegistersInternal System BusIPBusGPIOGIC8 HardwareSemaphoresEthernetDirectSlaveInterface(DSI)MemoryControllerGPIO PinsInterruptsRS-232MII/RMII/SMIIDSI Port32/System Bus32/DMABridgeFigure1. MSC8126 Block Diagram
AddressRegisterFileAddressALUEOnCE
Data ALURegisterFileDataALU
ProgramSequencerSC140CoreJTAGPowerManagement
SC140 Core
XaXbP
128
M1RAM
InstructionCacheQBus
128
PICIRQs
LICIRQs
MQBusSQBusLocal Bus
QBusBank 1
QBusBank 3
QBC
QBusInterface
128
128
Notes: 1. The arrows show the data transfer direction.
2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that definesfour QBus banks. In addition, the QBC handles internal memory contentions.
Figure2. StarCore SC140 DSP Extended Core Block Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Pin Assignments
1
1.1
Pin Assignments
FC-PBGA Ball Layout Diagrams
This section includes diagrams of the MSC8126 package ball grid array layouts and pinout allocation tables.
Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Pin Assignments
Top View
2
B
3
VDD
4
GND
5
GND
6
NMI_ OUT
7
GND
8
VDD
9
GND
10
VDD
11
GND
12
VDD
13
GND
14
VDD
15
GND
16
VDD
17
GND
18
VDD
19
GPIO0
20
VDD
21
VDD
22
GND
CGNDVDDTDO
S
GPIO28HCID1
RESETGND
VDDH
HCID2
GNDVDDGNDVDDGNDVDDGNDGNDGPIO30GPIO2GPIO1GPIO7GPIO3GPIO5GPIO6
DTDIEE0EE1HCID3GNDVDDGNDVDDGNDVDDVDDGPIO31GPIO29VDDHGPIO4VDDHGNDGPIO8
E
TCKTRSTTMSHRESETGPIO27HCID0GNDVDDGNDVDDGNDVDDGNDGNDVDDGNDGNDGPIO9GPIO13GPIO10GPIO12
F
PO RESETRST CONF
NMI HA29HA22GNDVDDVDDVDDBADDR 31
GNDVDDGNDVDDINT_ OUTETHRX_ETHTX_GPIO20GPIO18GPIO16GPIO11GPIO14GPIO19
CLKCLKETHCRSVDD
VDD
GHA24HA27HA25HA23HA17PWE0VDDVDDBM0ABBVDDCS1BCTL0GPIO15GNDGPIO17GPIO22
HHA20HA28VDDHA19TEST
PSD CAS
PGTAVDDBM1ARTRYAACKDBBHTATT4CS4GPIO24GPIO21VDDVDDHA31
JHA18HA26VDDHA13GND
PSDA BADDR MUX27
BADDR 30
VDDCLKINBM2DBGVDDGNDVDDTT3PSDA10BCTL1GPIO23GNDGPIO25A30
KHA15HA21HA16PWE3PWE1POERes.GNDGNDGNDGNDCLKOUTVDDTT2ALECS2GNDA26A29A28
LHA12HA14HA11VDDHVDDH
BADDR BADDR GND
2829VDDH
VDDHWBS
0VDDH
GNDGNDVDDHGNDGNDCS3VDDHA27A25A22
M81SCVDDH
HBRST
VDDH
MHD28HD31VDDHGNDGNDGNDGNDVDDHVDDHGNDA24A21
26NHD26HD30HD29HD24PWE2VDDHHWBS2HWBS4HWBS5D6
HBCSGNDGNDHRDSBGHCSCS0PSDWEGPIO26A23A20
PHD20HD27HD25HD23
HWBS3HWBS6HWBS7D3
HWBSHCLKIN1
GNDGNDSYNVCCSYNGNDGNDTABRTEA
PSDVAL
DP0VDDHGNDA19
RHD18VDDHGNDHD22TSZ1TSZ3GBLVDDVDDVDDTT0DP7DP6DP3TSDP2A17A18A16
THD17HD21HD1HD0TSZ0TSZ2TBSTVDDD16TT1D21D23DP5DP4DP1D30GNDA15A14
UHD16HD19HD2D2D8D9D11D14D15D17D19D22D25D26D28D31VDDHA12A13
VHD3VDDHGNDD0D1D4D5D7D10D12D13D18D20GNDD24D27D29A8A9A10A11
WHD6HD5HD4GNDGNDVDDHVDDHGNDHDST1HDST0VDDHGNDHD40VDDHHD33VDDHHD32GNDGNDA7A6
YHD7HD15VDDHHD9VDDHD60HD58GNDVDDHHD51GNDVDDHHD43GNDVDDHGNDHD37HD34VDDHA4A5
AAVDDHD14HD12HD10HD63HD59GNDVDDHHDHD52VDDHGNDVDDHHD46GNDHD42HD38HD35A0A2A3
ABGNDHD13HD11HD8HD62HD61HD57HD56HD55HD53HD50HD49HD48HD47HD45HD44HD41HD39HD36A1VDD
Figure3. MSC8126 Package, Top View
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Pin Assignments
Bottom View
22
B
GND
21
VDD
20
VDD
19
GPIO0
18
VDD
17
GND
16
VDD
15
GND
14
VDD
13
GND
12
VDD
11
GND
10
VDD
9
GND
8
VDD
7
GND
6
NMI_ OUT
5
GND
4
GND
3
VDD
2
CGPIO6GPIO5GPIO3GPIO7GPIO1GPIO2GPIO30GNDGNDVDDGNDVDDGNDVDDGNDHCID1GPIO28
S RESETGND
TDOVDDGND
DGPIO8GNDVDDHGPIO4VDDHGPIO29GPIO31VDDVDDGNDVDDGNDVDDGNDHCID3HCID2VDDHEE1EE0TDI
E
GPIO12GPIO10GPIO13GPIO9GNDGNDVDDGNDGNDVDDGNDVDDGNDVDDGNDHCID0GPIO27HRESETTMSTRSTTCK
FGPIO19GPIO14GPIO11GPIO16GPIO18GPIO20ETHTX_ETHRX_CLKCLKVDD
ETHCRSVDD
VDDINT_ OUTGNDVDDGNDVDDBADDR 31
VDDVDDGNDHA22HA29NMI
RST CONFPO RESETGGPIO22GPIO17GNDGPIO15BCTL0CS1VDDABBBM0VDDVDDPWE0HA17HA23HA25HA27HA24
HA31VDDHVDDGPIO21GPIO24CS4TT4HTADBBAACKARTRYBM1VDDPGTA
PSD CAS
TESTHA19VDDHA28HA20
JA30GPIO25GNDGPIO23BCTL1PSDA10TT3VDDGNDVDDDBGBM2CLKINVDD
BADDR PSDA 27MUXBADDR 30
GNDHA13VDDHA26HA18
KA28A29A26GNDCS2ALETT2VDDCLKOUTGNDGNDGNDGNDRes.POEPWE1PWE3HA16HA21HA15
LA22A25A27VDDHCS3GNDGNDVDDHGNDGNDGND
BADDR BADDR V
DDH
2928VDDHWBS0HWBS1
VDDH
VDDHHA11HA14HA12
MA21A24VDDHGNDVDDH
SC81VDDH
HBRST
26VDDHGNDGNDVDDHGNDGNDVDDHHD31HD28
MNA20A23GPIO26PSDWECS0HCSBGHRDSGNDGNDHBCSVDDHHWBS2HWBS4HWBS5D6
PWE2HD24HD29HD30HD26
PA19GNDVDDHDP0
PSDVAL
TEABRTAGNDGNDVCCSYNGNDSYNGNDHCLKINHWBS3HWBS6HWBS7D3
HD23HD25HD27HD20
RA16A18A17DP2TSDP3DP6DP7TT0VDDVDDVDDGBLTSZ3TSZ1HD22GNDVDDHHD18
TA14A15GNDD30DP1DP4DP5D23D21TT1D16VDDTBSTTSZ2TSZ0HD0HD1HD21HD17
UA13A12VDDHD31D28D26D25D22D19D17D15D14D11D9D8D2HD2HD19HD16
VA11A10A9A8D29D27D24GNDD20D18D13D12D10D7D5D4D1D0GNDVDDHHD3
WA6A7GNDGNDHD32VDDHHD33VDDHHD40GNDVDDHHDST0HDST1GNDVDDHVDDHGNDGNDHD4HD5HD6
YA5A4VDDHHD34HD37GNDVDDHGNDHD43VDDHGNDHD51VDDHGNDHD58HD60VDDHD9VDDHHD15HD7
AAA3A2A0HD35HD38HD42GNDHD46VDDHGNDVDDHHD52HDVDDHGNDHD59HD63HD10HD12HD14VDD
ABVDDA1HD36HD39HD41HD44HD45HD47HD48HD49HD50HD53HD55HD56HD57HD61HD62HD8HD11HD13GND
Figure4. MSC8126 Package, Bottom View
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Pin Assignments
1.2Signal List By Ball Location
Table1. MSC8126 Signal Listing by Ball Designator
Table1 presents signal list sorted by ball number. -
Des.
B3B4B5B6B7B8B9B10B11B12B13B14B15B16B17B18B19B20B21B22C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16C17
Signal Name
VDDGNDGNDNMI_OUTGNDVDDGNDVDDGNDVDDGNDVDDGNDVDDGNDVDD
GPIO0/CHIP_ID0/IRQ4/ETHTXD0
VDDVDDGNDGNDVDDTDOSRESET
GPIO28/DREQ2/UTXD
HCID1GNDVDDGNDVDDGNDVDDGNDGND
GPIO30/TIMER2/TMCLK/SDAGPIO2/TIMER1/CHIP_ID2/IRQ6
Des.
C18C19C20C21C22D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22E2E3E4E5E6E7E8E9E10E11
Signal Name
GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1
GPIO7/TDM3RCLK/IRQ5/ETHTXD3GPIO3/TDM3TSYN/IRQ1/ETHTXD2GPIO5/TDM3TDAT/IRQ3/ETHRXD3GPIO6/TDM3RSYN/IRQ4/ETHRXD2
TDIEE0EE1GNDVDDHHCID2HCID3/HA8
GNDVDDGNDVDDGNDVDDVDD
GPIO31/TIMER3/SCLGPIO29/CHIP_ID3/ETHTX_EN
VDDH
GPIO4/TDM3TCLK/IRQ2/ETHTX_ER
VDDHGND
GPIO8/TDM3RDAT/IRQ6/ETHCOL
TCKTRSTTMSHRESET
GPIO27/DREQ1/URXD
HCID0GNDVDDGNDVDD
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Pin Assignments
Table1. MSC8126 Signal Listing by Ball Designator (continued)
Des.
E12E13E14E15E16E17E18E19E20E21E22F2F3F4F5F6F7F8F9F10F11F12F13F14F15F16F17F18F19F20F21F22G2G3G4G5H21H22J2
Signal Name
GNDVDDGNDGNDVDDGNDGND
GPIO9/TDM2TSYN/IRQ7/ETHMDIOGPIO13/TDM2RCLK/IRQ11/ETHMDC
GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NCGPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC
PORESETRSTCONF
NMIHA29HA22GNDVDDVDDVDDGNDVDDGNDVDD
ETHRX_CLK/ETHSYNC_INETHTX_CLK/ETHREF_CLK/ETHCLOCK
GPIO20/TDM1RDATGPIO18/TDM1RSYN/DREQ2GPIO16/TDM1TCLK/DONE1/DRACK1GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXDGPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC
GPIO19/TDM1RCLK/DACK2
HA24HA27HA25HA23VDDHA31HA18
Des.
G6G7G8G9G10G11G12G13G14G15G16G17G18G19G20G21G22H2H3H4H5H6H7H8H9H10H11H12H13H14H15H16H17H18H19H20K15K16K17
Signal Name
HA17
PWE0/PSDDQM0/PBS0
VDDVDD
IRQ3/BADDR31BM0/TC0/BNKSEL0
ABB/IRQ4VDD
IRQ7/INT_OUTETHCRS/ETHRXD
VDDCS1BCTL0
GPIO15/TDM1TSYN/DREQ1
GND
GPIO17/TDM1TDAT/DACK1GPIO22/TDM0TCLK/DONE2/DRACK2
HA20HA28VDDHA19TESTPSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
VDD
BM1/TC1/BNKSEL1
ARTRYAACKDBB/IRQ5HTAVDDTT4/CS7CS4
GPIO24/TDM0RSYN/IRQ14
GPIO21/TDM0TSYN
VDDVDDTT2/CS5ALE
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Pin Assignments
Table1. MSC8126 Signal Listing by Ball Designator (continued)
Des.
J3J4J5J6J7J8J9J10J11J12J13J14J15J16J17J18J19J20J21J22K2K3K4K5K6K7K8K9K10K11K12K13K14M15M16M17M18M19M20
Signal Name
HA26VDDHA13GND
PSDAMUX/PGPL5
BADDR27VDDCLKIN
BM2/TC2/BNKSEL2
DBGVDDGNDVDDTT3/CS6PSDA10/PGPL0BCTL1/CS5
GPIO23/TDM0TDAT/IRQ13
GND
GPIO25/TDM0RCLK/IRQ15
A30HA15HA21HA16
PWE3/PSDDQM3/PBS3PWE1/PSDDQM1/PBS1POE/PSDRAS/PGPL2IRQ2/BADDR30ReservedGNDGNDGNDGNDCLKOUTVDDHHBRSTVDDHVDDHGNDVDDH
Des.
K18K19K20K21K22L2L3L4L5L6L7L8L9L10L14L15L16L17L18L19L20L21L22M2M3M4M5M6M7M8M9M10M14P12P13P14P15P16P17
Signal Name
CS2GNDA26A29A28HA12HA14HA11VDDHVDDHBADDR28IRQ5/BADDR29
GNDGNDGNDVDDHGNDGNDCS3VDDHA27A25A22HD28HD31VDDHGNDGNDVDDHVDDVDDHGNDGNDVCCSYNGNDGNDTABRTEA
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Pin Assignments
Table1. MSC8126 Signal Listing by Ball Designator (continued)
Des.
M21M22N2N3N4N5N6N7N8N9N10N14N15N16N17N18N19N20N21N22P2P3P4P5P6P7P8P9P10P11T6T7T8T9T10T11T12T13T14
Signal Name
A24A21HD26HD30HD29HD24
PWE2/PSDDQM2/PBS2
VDDH
HWBS0/HDBS0/HWBE0/HDBE0
HBCSGNDGND
HRDS/HRW/HRDE
BGHCSCS0PSDWE/PGPL1GPIO26/TDM0RDAT
A23A20HD20HD27HD25HD23
HWBS3/HDBS3/HWBE3/HDBE3HWBS2/HDBS2/HWBE2/HDBE2HWBS1/HDBS1/HWBE1/HDBE1
HCLKINGNDGNDSYN
HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5
TSZ0TSZ2TBSTVDDD16TT1D21
Des.
P18P19P20P21P22R2R3R4R5R6R7R8R9R10R11R12R13R14R15R16R17R18R19R20R21R22T2T3T4T5U21U22V2V3V4V5V6V7V8
Signal Name
PSDVAL
DP0/DREQ1/EXT_BR2
VDDHGNDA19HD18VDDHGNDHD22
HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4
TSZ1TSZ3IRQ1/GBLVDDVDDVDDTT0/HA7IRQ7/DP7/DREQ4IRQ6/DP6/DREQ3IRQ3/DP3/DREQ2/EXT_BR3
TS
IRQ2/DP2/DACK2/EXT_DBG2
A17A18A16HD17HD21HD1/DSISYNCHD0/SWTE
A12A13HD3/MODCK1
VDDHGNDD0D1D4D5
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Pin Assignments
Table1. MSC8126 Signal Listing by Ball Designator (continued)
Des.
T15T16T17T18T19T20T21T22U2U3U4U5U6U7U8U9U10U11U12U13U14U15U16U17U18U19U20W15W16W17W18W19W20W21W22Y2Y3Y4Y5
Signal Name
D23
IRQ5/DP5/DACK4/EXT_BG3IRQ4/DP4/DACK3/EXT_DBG3IRQ1/DP1/DACK1/EXT_BG2
D30GNDA15A14HD16HD19HD2/DSI
D2D3D6D8D9D11D14D15D17D19D22D25D26D28D31VDDHVDDH
HD33/D33/reserved
VDDH
HD32/D32/reserved
GNDGNDA7A6HD7HD15VDDHHD9
Des.
V9V10V11V12V13V14V15V16V17V18V19V20V21V22W2W3W4W5W6W7W8W9W10W11W12W13W14AA9AA10AA11AA12AA13AA14AA15AA16AA17AA18AA19AA20
Signal Name
D7D10D12D13D18D20GNDD24D27D29A8A9A10A11HD6HD5/CNFGSHD4/MODCK2
GNDGNDVDDHVDDHGNDHDST1/HA10HDST0/HA9
VDDHGND
HD40/D40/ETHRXD0
VDDH
HD/D/ETHTX_EN
HD52/D52VDDHGNDVDDH
HD46/D46/ETHTXT0
GND
HD42/D42/ETHRXD2/reserved
HD38/D38/reservedHD35/D35/reserved
A0
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Pin Assignments
Table1. MSC8126 Signal Listing by Ball Designator (continued)
Des.
Y6Y7Y8Y9Y10Y11Y12Y13Y14Y15Y16Y17Y18Y19Y20Y21Y22AA2AA3AA4AA5AA6AA7AA8
Signal Name
VDD
HD60/D60/ETHCOL/reserved
HD58/D58/ETHMDC
GNDVDDHHD51/D51GNDVDDH
HD43/D43/ETHRXD3/reserved
GNDVDDHGND
HD37/D37/reservedHD34/D34/reserved
VDDHA4A5VDDHD14HD12HD10HD63/D63HD59/D59/ETHMDIO
GND
Des.
AA21AA22AB2AB3AB4AB5AB6AB7AB8AB9AB10AB11AB12AB13AB14AB15AB16AB17AB18AB19AB20AB21AB22
Signal Name
A2A3GNDHD13HD11HD8HD62/D62HD61/D61HD57/D57/ETHRX_ER
HD56/D56/ETHRX_DV/ETHCRS_DVHD55/D55/ETHTX_ER/reserved
HD53/D53HD50/D50
HD49/D49/ETHTXD3/reservedHD48/D48/ETHTXD2/reserved
HD47/D47/ETHTXD1
HD45/D45HD44/D44HD41/D41/ETHRXD1HD39/D39/reservedHD36/D36/reserved
A1VDD
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Electrical Characteristics
2Electrical Characteristics
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8126 Reference Manual.
2.1Maximum Ratings
CAUTION
This device contains circuitry protecting against damagedue to high static voltage or electrical fields; however,normal precautions should be taken to avoid exceedingmaximum voltage ratings. Reliability is enhanced if unusedinputs are tied to an appropriate logic voltage level (forexample, either GND or VDD).
In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist.Table2 describes the maximum electrical ratings for the MSC8126.
Table2. Absolute Maximum Ratings
Rating
Core and PLL supply voltageI/O supply voltageInput voltage
Maximum operating temperature:• 400 MHz• 500 MHz
Minimum operating temperature• 400 MHz• 500 MHz
Storage temperature rangeNotes:
1.2.3.
Symbol
VDDVDDHVINTJ
Value
–0.2 to 1.6–0.2 to 4.0–0.2 to 4.0
10590–400–55 to +150
Unit
VVV°C°C°C°C°C
TJ
TSTG
Functional operating conditions are given in Table3.
Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage.
Section 3.5, Thermal Considerations includes a formula for computing the chip junction temperature (TJ).
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Electrical Characteristics
2.2Recommended Operating Conditions
Table3. Recommended Operating Conditions
Rating
Symbol
VCCSYNVDD
Table3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
ValueUnit
Core and PLL supply voltage:• Standard— 400 MHz— 500 MHz
• Reduced (300 and 400 MHz)I/O supply voltageInput voltage
Operating temperature range:• Standard• Extended
1.14 to 1.261.16 to 1.241.07 to 1.133.135 to 3.465–0.2 to VDDH+0.2
0 to 90–40 to 105
VVVVV°C°C
VDDHVINTJTJ
2.3Thermal Characteristics
Table4. Thermal Characteristics for the MSC8126
FC-PBGA 20 × 20 mm5
Natural Convection
200 ft/min (1 m/s) airflow
2115
°C/W°C/W°C/W°C/W°C/W
Table4 describes thermal characteristics of the MSC8126 for the FC-PBGA packages.
CharacteristicSymbolUnit
Junction-to-ambient1, 2
Junction-to-ambient, four-layer board1, 3Junction-to-board (bottom)4Junction-to-case5
Junction-to-package-top6Notes:
1.
RθJARθJARθJBRθJCΨJT
261990.91
2.3.4.5.6.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.
Section 3.5, Thermal Considerations provides a detailed explanation of these characteristics.
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Electrical Characteristics
2.4DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8126. The measurements in Table5 assume the following system conditions:
••
TA = 25 °CVDD =
—400 MHz = 1.14–1.26 VDC—500 MHz = 1.16–1.24 VDC
VDDH = 3.3 V ± 5% VDCGND = 0 VDC
••
Note:The leakage current is measured for nominal VDDH and VDD.
Table5. DC Electrical Characteristics
Characteristic
Input high voltage1, all inputs except CLKINInput low voltage1CLKIN input high voltageCLKIN input low voltage
Input leakage current, VIN = VDDH
Tri-state (high impedance off state) leakage current, VIN = VDDHSignal low input current, VIL = 0.4 V2Signal high input current, VIH = 2.0 V2Output high voltage, IOH = –2 mA,except open drain pins
Output low voltage, IOL= 3.2 mAVCCSYN PLL supply currentInternal supply current:•Wait mode•Stop mode
Typical power 400 MHz at 1.2 V4Notes:
1.2.3.4.
Symbol
VIHVILVIHCVILCIINIOZILIHVOHVOLIVCCSYNIDDWIDDSP
Min
2.0GND2.4GND–1.0–1.0–1.0–1.02.0—————
Typical
—03.000.090.090.090.093.002375329031.15
Max
3.4650.43.4650.41111—0.44———
Unit
VVVVµAµAµAµAVVmAmAmAW
See Figure 5 for undershoot and overshoot voltages.Not tested. Guaranteed by design.
Measured for 1.2 V core at 25°C junction temperature.
The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and all four cores. It was created using CodeWarrior® 2.5. These values are provided as examples only. Power consumption is application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 of this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601).
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Electrical Characteristics
VIH
VDDH + 17%VDDH + 8%
VDDH
VIL
GND
GND – 0.3 VGND – 0.7 V
Must not exceed 10% of clock period
Figure5. Overshoot/Undershoot Voltage for VIH and VIL
2.5AC Timings
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay. When calculating overall loading, also consider additional RC delay.
2.5.1Output Buffer Impedances
Table6. Output Buffer Impedances
Output Buffers
Typical Impedance (Ω)
505050
System busMemory controllerParallel I/ONote:
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
2.5.2Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3 describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the following guidelines when starting up an MSC8126 device:
••••Note:
PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table11 for timing.
If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDD levels and then the VDDH levels (see Figure 7).
CLKIN should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before PORESET deassertion to guarantee correct device operation (see Figure 6 and Figure 7).
CLKIN must not be pulled high during VDDH power-up. CLKIN can toggle during this period.See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power supply design recommendations.
The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which VDD and VDDH are raised together. Figure 7 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle as VDDH rises.
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Electrical Characteristics
VDDH = Nominal ValueVDD = Nominal Value13.3 VVDDH Nominal Level
Voltage2.2 V1.2 Vo.5 V
VDD Nominal Level
Time
CLKIN Starts TogglingPORESET/TRST AssertedVDD/VDDH Applied
PORESET/TRST DeassertedFigure6. Start-Up Sequence: VDD and VDDH Raised Together
VDDH = Nominal VDD = Nominal
1
3.3 VVDDH Nominal
Voltage1.2 Vo.5 V
VDD Nominal
Time
PORESET/TRST asserted
VDD applied
CLKIN starts togglingVDDH applied
PORESET/TRST deasserted
Figure7. Start-Up Sequence: VDD Raised Before VDDH with CLKIN Started with VDDH
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Electrical Characteristics
In all cases, the power-up sequence must follow the guidelines shown in Figure 8.
V3.3 V
B
A
VDDH (IO)
1.2 V
VDD/VCCSYN
t (time)Figure8. Power-Up Sequence for VDDH and VDD/VCCSYN
The following rules apply:
1.2.
During time interval A, VDDH should always be equal to or less than the VDD/VCCSYN voltage level.The duration of interval A should be kept below 10 ms.
The duration of timing interval B should be kept as small as possible and less than 10 ms.
2.5.3Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table7 shows the maximum frequency values for internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum frequency values are not exceeded.
Table7. Maximum Frequencies
Core frequency
Reference frequency (REFCLK)Internal bus frequency (BLCK)DSI clock frequency (HCLKIN)
External clock frequency (CLKIN or CLKOUT)
400/500133/166133/166
HCLKIN ≤ (min{100 MHz, CLKOUT})
133/166
Characteristic Maximum in MHz
Table8. Clock Frequencies
Characteristics
CLKIN frequencyBCLK frequency
Reference clock (REFCLK) frequencyOutput clock (CLKOUT) frequencySC140 core clock frequencyNote:
Symbol
FCLKINFBCLKFREFCLKFCLKOUTFCORE
400 MHz DeviceMin
20404040200
500 MHz DeviceMin
20404040200
Max
133.3133.3133.3133.3400
Max
166.7166.7166.7166.7500
The rise and fall time of external clocks should be 5ns maximum
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Electrical Characteristics
Table9. System Clock Parameters
Characteristic MinPhase jitter between BCLK and CLKINCLKIN frequencyCLKIN slope
PLL input clock (after predivider)PLL output frequency (VCO output)•400 MHz core•500 MHz coreCLKOUT frequency jitter1CLKOUT phase jitter1 with CLKIN phase jitter of ±100 psNotes:
1.2.
Peak-to-peak.
Not tested. Guaranteed by design.
—20—20800
16002000
——
200500
Max
0.3see Table8
3100
Unit
nsMHznsMHzMHzMHzMHzpsps
2.5.4
••••••
Reset Timing
Power-on reset (PORESET)External hard reset (HRESET)External soft reset (SRESET)Software watchdog resetBus monitor reset
Host reset command through JTAG
The MSC8126 has several inputs to the reset logic:
All MSC8126 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table10 describes the reset sources.
Table10. Reset Sources
Name DirectionPower-on reset(PORESET)
Input
Description
Initiates the power-on reset flow that resets the MSC8126 and configures various attributes of the MSC8126. On PORESET, the entire MSC8126 device is reset. SPLL states is reset, HRESET and SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI bits port or a System Bus bits port are configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC8126. While HRESET is asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The most configurable features are reconfigured. These features are defined in the 32-bit hard reset configuration word described in Hard Reset Configuration Word section of the Reset chapter in the MSC8126 Reference Manual.
Initiates the soft reset flow. The MSC8126 detects an external assertion of SRESET only if it occurs while the MSC8126 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is driven, the SC140 extended cores are reset, and system configuration is maintained.
When the MSC8126 watchdog count reaches zero, a software watchdog reset is signalled. The enabled software watchdog event then generates an internal hard reset sequence.
When the MSC8126 bus monitor count reaches zero, a bus monitor hard reset is asserted. The enabled bus monitor event then generates an internal hard reset sequence.
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the soft reset signal and an internal soft reset sequence is generated.
External hard reset (HRESET)
Input/ Output
External soft reset (SRESET)Software
watchdog resetBus monitor resetHost reset
command through the TAP
Input/ Output
InternalInternalInternal
Table11 summarizes the reset actions that occur as a result of the different reset sources.
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Electrical Characteristics
Table11. Reset Actions for Each Reset Source
Power-On Reset (PORESET)External only
Configuration pins sampled (Refer to Section 2.5.4.1 for details).SPLL state reset
System reset configuration write through the DSI
System reset configuration write though the system busHRESET drivenSIU registers reset
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and GPIO)
SRESET driven
SC140 extended cores resetMQBS reset
YesYesYesYesYesYesYes
Hard Reset (HRESET)External or Internal (Software Watchdog or
Bus Monitor)
NoNoNoYesYesYesYes
Soft Reset (SRESET)
JTAG Command: EXTEST, CLAMP, or
HIGHZ
NoNoNoNoNoNoYes
Reset Action/Reset Source
External
NoNoNoNoNoNoYes
YesYesYes
YesYesYes
YesYesYes
Depends on command
YesYes
2.5.4.1Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after VDD and VDDH are both at their nominal levels.
2.5.4.2
••
Reset Configuration
The MSC8126 has two mechanisms for writing the reset configuration:
Through the direct slave interface (DSI)
Through the system bus. When the reset configuration is written through the system bus, the MSC8126 acts as a configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is written, a default configuration word is applied.
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset Configuration Mode and boot and operating conditions:
••••••••
RSTCONF CNFGS DSISYNC DSI CHIP_ID[0–3] BM[0–2] SWTE MODCK[1–2]
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2.5.4.3Reset Timing Tables
Table12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or through the system bus.
Table12. Timing for a Reset Configuration Write through the DSI or System Bus
No.
1
Characteristics
Required external PORESET duration minimum•CLKIN = 20 MHz
•CLKIN = 133 MHz (400 MHz core)•CLKIN = 166 MHz (500 MHz core)
Delay from deassertion of external PORESET to deassertion of internal PORESET
•CLKIN = 20 MHz to 166 MHz
Delay from de-assertion of internal PORESET to SPLL lock•CLKIN = 20 MHz (RDF = 1)
•CLKIN = 133 MHz (RDF = 2) (400 MHz core)•CLKIN = 166 MHz (RDF = 2) (500 MHz core)Delay from SPLL to HRESET deassertion•REFCLK = 40 MHz to 166 MHz
Delay from SPLL lock to SRESET deassertion•REFCLK = 40 MHz to 166 MHz
Setup time from assertion of RSTCONF, CNFGS, DSISYNC, DSI, CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of PORESET
Hold time from deassertion of PORESET to deassertion of RSTCONF, CNFGS, DSISYNC, DSI, CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2]
Timings are not tested, but are guaranteed by design.
Expression
16/CLKIN
Min
80012096
Max
800——
Unit
nsnsns
21024/CLKIN
6.17
00/(CLKIN/RDF)(PLL reference clock-division factor)
32096773.083.103
51.2320967712.812.88—
µsµsµsµsµsµsns
3
567
512/REFCLK515/REFCLK
85—ns
Note:
1
RSTCONF, CNFGS, DSISYNC, DSI
CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]pins are sampledHost programsReset Configuration
Word
SPLL is locked
(no external indication)
PORESETInputPORESET Internal
1 + 2
MODCK[3–5]
HRESETOutput (I/O)
2
3
SRESETOutput (I/O)
Reset configuration write sequence during this period.
SPLL
lockingperiod
56
Figure9. Timing Diagram for a Reset Configuration Write
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Electrical Characteristics
2.5.5
2.5.5.1
System Bus Access Timing
Core Data Transfers
Generally, all MSC8126 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table13 shows.
Table13. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)
BCLK/SC140 clock
T2
1:4, 1:6, 1:8, 1:10
1:31:5
1/4 REFCLK1/6 REFCLK2/10 REFCLK
T3
1/2 REFCLK1/2 REFCLK1/2 REFCLK
T4
3/4 REFCLK4/6 REFCLK7/10 REFCLK
Figure 10 is a graphical representation of Table13.
REFCLK
T1
REFCLK
T1
T2
T3
T4
T2
T3
T4
for 1:3
for 1:4, 1:6, 1:8, 1:10
REFCLK
T1
T2
T3
T4
for 1:5
Figure10. Internal Tick Spacing for Memory Controller Signals
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Electrical Characteristics
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge.
Table14. AC Timing for SIU Inputs
Value for Bus Speed in MHz
No.
Characteristic
Ref = CLKIN133 1661011a11b11c11d
Hold time for all signals after the 50% level of the REFCLK rising edgeARTRY/ABB set-up time before the 50% level of the REFCLK rising edge
DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising edge
AACK set-up time before the 50% level of the REFCLK rising edgeTA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge
•Data-pipeline mode•Non-pipeline mode
Data bus set-up time before REFCLK rising edge in Normal mode•Data-pipeline mode•Non-pipeline mode
Data bus set-up time before the 50% level of the REFCLK rising edge in ECC and PARITY modes•Data-pipeline mode•Non-pipeline mode
DP set-up time before the 50% level of the REFCLK rising edge•Data-pipeline mode•Non-pipeline mode
TS and Address bus set-up time before the 50% level of the REFCLK rising edge
•Extra cycle mode (SIUBCR[EXDD] = 0)•No extra cycle mode (SIUBCR[EXDD] = 1)
Address attributes: TT/TBST/TSZ/GBL set-up time before the 50% level of the REFCLK rising edge
•Extra cycle mode (SIUBCR[EXDD] = 0)•No extra cycle mode (SIUBCR[EXDD] = 1)
PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge
IRQx setup time before the 50% level; of the REFCLK rising edge3IRQx minimum pulse width31.2.3.
0.53.03.32.9
0.53.03.32.9
Ref = CLKOUT133
0.53.03.32.9
Units
nsnsnsns
3.44.01.84.0
3.44.01.74.0
3.44.01.84.0
nsnsnsns
12
131
2.07.32.06.1
2.07.32.06.1
2.07.32.06.1
nsnsnsns
141
15a
3.65.03.65.03.85.0nsns
15b
3..43.74.06.0 + TREFCLK
3..43.74.06.0 + TREFCLK
3..43.74.06.0 + TREFCLK
nsnsnsnsns
161718Notes:
Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.Guaranteed by design
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Table15. AC Timing for SIU Outputs
Value for Bus Speed in MHz
No.
Characteristic
Ref = CLKIN133
3023132a
Minimum delay from the 50% level of the REFCLK for all signalsPSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge
Address bus max delay from the 50% level of the REFCLK rising edge
•Multi-master mode (SIUBCR[EBM] = 1)•Single-master mode (SIUBCR[EBM] = 0)
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50% level of the REFCLK rising edge
Address attributes: TT[2–4]/TC max delay from the 50% level of the REFCLK rising edge
BADDR max delay from the 50% level of the REFCLK rising edgeData bus max delay from the 50% level of the REFCLK rising edge•Data-pipeline mode•Non-pipeline mode
DP max delay from the 50% level of the REFCLK rising edge•Data-pipeline mode•Non-pipeline mode
Memory controller signals/ALE/CS[0–4] max delay from the 50% level of the REFCLK rising edge
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising edge
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the REFCLK rising edge1.2.3.4.
0.84.9
Ref = CLKOUT
166
0.84.9
Units
133
1.05.8
nsns
5..25.15.74.23.96.15.36..24.74.5
5.53.95.15.74.23.76.15.36.53.94.74.5
6.45.16.06.65.14.87.06.27.45.15.65.4
nsnsnsnsnsnsnsnsnsnsnsns
32b32c32d33a
33b
3435a35bNotes:
Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except where otherwise specified.
The load for specification 30 is 10 pF. The load for the other specifications in this table is 20 pF. For a 15 pF load, subtract 0.3 ns from the listed value.
The maximum bus frequency depends on the mode:
In 60x-compatible mode connected to another MSC8126 device, the frequency is determined by adding the input and output longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8126.
• To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details.
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Electrical Characteristics
REFCLK
10
AACK/ARTRY/TA/TEA/DBG/BG/BR PSDVAL/ABB/DBB inputs
11
10
12
Data bus inputs—normal mode
10
Data bus inputs—ECC and parity modes
DP inputs
Address bus/TS /TT[0–4]/TC[0–2]/
TBST/TSZ[0–3]/GBL inputs
PUPMWAIT input
1314151617
IRQx inputs
30
Min delay for all output pins
31
PSDVAL/TEA/TA outputs
Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs
32a/b
1810
BADDR outputs
32c33a
Data bus outputs
DP outputs
33b
Memory controller/ALE outputs
34
35
AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs
Figure11. SIU Timing Diagram
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Electrical Characteristics
2.5.5.2CLKIN to CLKOUT Skew
Table16. CLKOUT Skew
Table17 describes the CLKOUT-to-CLKIN skew timing.
No.
202122Notes:
Rise-to-rise skewFall-to-fall skew
Characteristic Min1
0–0.82.8
Max1
0.851.0—
Units
nsnsns
CLKOUT phase high and low (1.2 V, 133 MHz)1.2.3.4.
A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.CLKOUT skews are measured using a load of 10 pF.
CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.
For designs that use the CLKOUT synchronization mode, use the skew values listed in Table16 to adjust the rise-to-fall timing values specified for CLKIN synchronization. Figure 12 shows the relationship between the CLKOUT and CLKIN timings.
CLKINCLKOUT
20
21
Figure12. CLKOUT and CLKIN Signals.
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Electrical Characteristics
2.5.5.3DMA Data Transfers
Table17. DMA Signals
Table17 describes the DMA signal timing.
No.
3738394041
Characteristic
DREQ set-up time before the 50% level of the falling edge of REFCLKDREQ hold time after the 50% level of the falling edge of REFCLKDONE set-up time before the 50% level of the rising edge of REFCLKDONE hold time after the 50% level of the rising edge of REFCLK
DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge
Ref = CLKINMin
5.00.55.00.50.5
Ref = CLKOUT(1.2 V only)Min
5.00.55.00.50.5
Units
nsnsnsnsns
Max
————7.5
Max
————8.4
The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ
according to the timings in Table17. Figure 13 shows synchronous peripheral interaction.
REFCLK
38
37
DREQ
40
39
DONE
41
DACK/DONE/DRACK
Figure13. DMA Signals
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Electrical Characteristics
2.5.6DSI Timing
The timings in the following sections are based on a 20 pF capacitive load.
2.5.6.1 DSI Asynchronous Mode
Table18. DSI Asynchronous Mode Timing
Characteristics
Min
1.51.3
No.
100101102
Max
———
Unit
nsns
Attributes1 set-up time before strobe (HWBS[n]) assertionAttributes1 hold time after data strobe deassertionRead/Write data strobe deassertion width:•DCR[HTAAD] = 1
— Consecutive access to the same DSI— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11•DCR[HTAAD] = 0
Read data strobe deassertion to output data high impedance
Read data strobe assertion to output data active from high impedanceOutput data hold time after read data strobe deassertion
Read/Write data strobe assertion to HTA active from high impedanceOutput data valid to HTA assertion
Read/Write data strobe assertion to HTA valid2•1.1Vcore•1.2Vcore
Read/Write data strobe deassertion to output HTA high impedance.(DCR[HTAAD] = 0, HTA at end of access released at logic 0)Read/Write data strobe deassertion to output HTA deassertion.(DCR[HTAAD] = 1, HTA at end of access released at logic 1)Read/Write data strobe deassertion to output HTA high impedance.(DCR[HTAAD] = 1, HTA at end of access released at logic 1•DCR[HTADT] = 01•DCR[HTADT] = 10•DCR[HTADT] = 11
Read/Write data strobe assertion width
Host data input set-up time before write data strobe deassertionHost data input hold time after write data strobe deassertion•1.1Vcore•1.2Vcore1.2.3.
1.8 + TREFCLK5 + TREFCLK
5 + (1.5 × TREFCLK)5 + (2.5 × TREFCLK)1.8 + TREFCLK
—2.02.22.23.2—————
5 + TREFCLK
5 + (1.5 × TREFCLK)5 + (2.5 × TREFCLK)
1.8 + TREFCLK
1.01.71.5
————8.5————7.46.76.56.5
nsnsnsnsnsnsnsnsnsnsnsnsnsns
103104105106107108
109110111
nsnsnsnsnsnsns
112201202
Notes:
Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.All values listed in this table are tested or guaranteed by design.
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Electrical Characteristics
Figure 14 shows DSI asynchronous read signals timing.
HCSHA[11–29]HCID[0–4]
HDSTHRW1HWBSn2
100101
112
HDBSn
1HRDS2103
102
107
104
HD[0–63]
106
105
109
HTA3108
110
HTA4111
Notes:
1.2.3.4.
Used for single-strobe mode access.Used for dual-strobe mode access.
HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation.
HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
Figure14. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram
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Electrical Characteristics
Figure 15 shows DSI asynchronous write signals timing.
HCSHA[11–29]HCID[0–4]
HDSTHRW1HRDS2
100
101
112
HDBSn1HWBSn2201
202
HD[0–63]
109
102
106
HTA3108
110
HTA4111
Notes:
1.2.3.4.
Used for single-strobe mode access.Used for dual-strobe mode access.
HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation.HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
Figure15. Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram
Figure 16 shows DSI asynchronous broadcast write signals timing.
HCSHA[11–29]HCID[0–4]
HDSTHRW1HRDS2
100
112
101
HDBSn1HWBSn2
201
202
HD[0–63]Notes:
1.2.
Used for single-strobe mode access.Used for dual-strobe mode access.
102
Figure16. Asynchronous Broadcast Write Timing Diagram
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Electrical Characteristics
2.5.6.2 DSI Synchronous Mode
Table19. DSI Inputs—Synchronous Mode
No.
120121122123124125126127Notes:
Characteristic ExpressionHCLKIN Cycle Time1, 2HCLKIN high Pulse WidthHCLKIN low Pulse WidthHA[11–29] inputs set-up timeHD[0–63] inputs set-up timeHCID[0–4] inputs set-up timeAll other inputs set-up timeAll inputs hold time1.2.
Values are based on a frequency range of 18–100 MHz.Refer to Table7 for HCLKIN frequency limits.
HTC(0.5 ± 0.1) × HTC(0.5 ± 0.1) × HTC
—————
Min
10.04.04.01.20.41.31.21.5
Max
55.633.333.3—————
Units
nsnsnsnsnsnsnsns
Table20. DSI Outputs—Synchronous Mode
No.
128129130131132133134135
HCLKIN high to HD[0–63] output activeHCLKIN high to HD[0–63] output validHD[0–63] output hold time
HCLKIN high to HD[0–63] output high impedanceHCLKIN high to HTA output activeHCLKIN high to HTA output validHTA output hold time
HCLKIN high to HTA high impedance
Characteristic Min2.0—1.7—2.0—1.7—
Max
—6.3—7.6—5.9—6.3
Units
nsnsnsnsnsnsnsns
120
122
HCLKIN
123
HA[11–29] input signals
124
HD[0–63] input signals
125
HCID[0–4] input signals
126
All other input signals
129
121127
127
127
127
131130
HD[0–63] output signals
~~~~128
133
132
135134
Figure17. DSI Synchronous Mode Signals Timing Diagram
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Electrical Characteristics
2.5.7TDM Timing
Table21. TDM Timing
Ref = CLKINMin
771.31.02.8—2.5——2.5
No.
300301302303304305306307308309310Notes:
TDMxRCLK/TDMxTCLK
Characteristic ExpressionTC1(0.5 ± 0.1) × TC(0.5 ± 0.1) × TC
Max
—————8.8—10.58.5—
Units
nsnsnsnsnsnsnsnsnsnsns
16 —TDMxRCLK/TDMxTCLK high pulse widthTDMxRCLK/TDMxTCLK low pulse widthTDM receive all input set-up timeTDM receive all input hold time
TDMxTCLK high to TDMxTDAT/TDMxRCLK output active2,3TDMxTCLK high to TDMxTDAT/TDMxRCLK output valid2,3All output hold time5TDMxTCLK high to TDmXTDAT/TDMxRCLK output high impedance2,3TDMxTCLK high to TDMXTSYN output valid2TDMxTSYN output hold time51.2.3.4.5.
Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz. Values are based on 20 pF capacitive load.
When configured as an output, TDMxRCLK acts as a second data link. See the MSC8126 Reference Manual for details.CLKOUT synchronization is not supported for cores operating at above 400 MHz.Values are based on 10 pF capacitive load.
300
301
TDMxRCLK
304
303
TDMxRDAT
304
302
303
TDMxRSYN
Figure18. TDM Inputs Signals
300
301
TDMxTCLK
306
302
308
~~~~305
TDMxTDAT
TDMxRCLK
309
TDMxTSYN
307
310
Figure19. TDM Output Signals
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2.5.8
No.
400401402
UART Timing
Table22. UART Timing
Characteristics
URXD and UTXD inputs high/low duration URXD and UTXD inputs rise/fall timeUTXD output rise/fall time
Expression
16 × TREFCLK
Min
160.0Max
—1010
Unit
nsnsns
401
UTXD, URXD inputs
400
401
400
Figure20. UART Input Timing
402UTXD output 402Figure21. UART Output Timing
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2.5.9
No.
500501502503
Timer Timing
Table23. Timer Timing
Characteristics
TIMERx frequencyTIMERx Input high periodTIMERx Output low period
TIMERx Propagations delay from its clock input•1.1Vcore•1.2Vcore
Ref = CLKINMin
10.04.04.03.12.8
Max
———9.58.1
Unit
nsnsnsnsns
500501502TIMERx (Input)
503
TIMERx (Output)
Figure22. Timer Timing
2.5.10
2.5.10.1
Ethernet Timing
Management Interface Timing
Table24. Ethernet Controller Management Interface Timing
No.
801802
Characteristics
ETHMDIO to ETHMDC rising edge set-up timeETHMDC rising edge to ETHMDIO hold time
Min
1010
Max
——
Unit
nsns
ETHMDC
801802
ETHMDIO
Valid
Figure23. MDIO Timing Relationship to MDC
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2.5.10.2
No.
803804805
MII Mode Timing
Table25. MII Mode Signal Timing
Characteristics
Min
3.53.511
Max
——14.612.6
Unit
nsnsnsns
ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up timeETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3], ETHRX_ER hold timeETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay•1.1Vcore•1.2Vcore
ETHRX_CLK
803
ETHRX_DVETHRXD[0–3]ETHRX_ER
Valid
804
ETHTX_CLK
805
ETHTX_ENETHTXD[0–3] ETHTX_ER
ValidValid
Figure24. MII Mode Signal Timing
2.5.10.3 RMII Mode
Table26. RMII Mode Signal Timing
No.
806807811
Characteristics
ETHTX_EN,ETHRXD[0–1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising edge set-up time
ETHREF_CLK rising edge to ETHRXD[0–1], ETHCRS_DV, ETHRX_ER hold time
ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay.
1.1 V CoreMin
1.61.63
1.2 V CoreMin
21.63
Max
——12.5
Max
——11
Unit
nsnsns
ETHREF_CLK
806
ETHCRS_DVETHRXD[0–1]ETHRX_ER
Valid
811
ETHTX_ENETHTXD[0–1]
807
ValidValid
Figure25. RMII Mode Signal Timing
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2.5.10.4SMII Mode
Table27. SMII Mode Signal Timing
No.
808809810
Characteristics
ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up timeETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold timeETHCLOCK rising edge to ETHSYNC, ETHTXD output delay•1.1 V core.•1.2 V core.1.2.
Measured using a 5 pF load.Measured using a 15 pF load.
Min
1.01.01.511.51
Max
——6.025.02
Unit
nsnsnsns
Notes:
ETHCLOCK
808
ETHSYNC_INETHRXD
809
Valid
810
ETHSYNCETHTXD
ValidValid
Figure26. SMII Mode Signal Timing
2.5.11
No.
601602603604605
GPIO Timing
Table28. GPIO Timing
Characteristics
REFCLK edge to GPIO out valid (GPIO out delay time)REFCLK edge to GPIO out not valid (GPIO out hold time)REFCLK edge to high impedance on GPIO outGPIO in valid to REFCLK edge (GPIO in set-up time)REFCLK edge to GPIO in not valid (GPIO in hold time)
Ref = CLKINMin
—1.1—3.50.5
Ref = CLKOUTMin
—1.3—3.70.5
Max
6.1—5.4——
Max
6.9—6.2——
Unit
nsnsnsnsns
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REFCLK
601603GPIO(Output)
High Impedance
602604GPIO(Input)
605Valid
Figure27. GPIO Timing
2.5.12EE Signals
Table29. EE Pin Timing
Number
6566
Notes:
1.2.
Characteristics TypeEE0 (input)EE1 (output)
AsynchronousSynchronous to Core clock
Min
4 core clock periods1 core clock period
The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset. Refer to Table 1-4 on page 1-6 for details on EE pin functionality.
Figure 28 shows the signal behavior of the EE pins.
65
EE0 in
66
EE1 out
Figure28. EE Pin Timing
2.5.13JTAG Signals
Table30. JTAG Timing
No.
700701702
Characteristics
TCK frequency of operation (1/(TC × 4); maximum 25 MHz)TCK cycle time
TCK clock pulse width measured at VM = 1.6 V•High•Low
TCK rise and fall times
All frequenciesMin Max0.040.020.016.00.0
25———3.0
Unit
MHznsnsnsns
703
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Table30. JTAG Timing (continued)
No.
704705706707708709710711712713Note:
Boundary scan input data set-up timeBoundary scan input data hold timeTCK low to output data valid TCK low to output high impedanceTMS, TDI data set-up timeTMS, TDI data hold timeTCK low to TDO data validTCK low to TDO high impedanceTRST assert time
TRST set-up time to TCK low
All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
Characteristics
All frequenciesMin Max5.020.00.00.05.020.00.00.0100.030.0
——30.030.0——20.020.0——
Unit
nsnsnsnsnsnsnsnsnsns
701
702
TCK(Input)
VIH703
VM
VIL
703
VM
Figure29. Test Clock Input Timing Diagram
VIH
704
DataInputs
706
DataOutputs
707
DataOutputs
Output Data Valid
Input Data Valid
705
TCK(Input)
VIL
Figure30. Boundary Scan (JTAG) Timing Diagram
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TCK(Input)TDITMS(Input)
VIH
VIL
708
Input Data Valid
710
709
TDO(Output)
711
TDO(Output)
Output Data Valid
Figure31. Test Access Port Timing Diagram
TCK(Input)
713
TRST(Input)
712
Figure32. TRST Timing Diagram
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Hardware Design Considerations
3
3.1
•••
Hardware Design Considerations
Start-up Sequencing Recommendations
Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the required minimum power levels. This can be implemented via weak pull-down resistors.
CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels.If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up VDDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring both voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down first and then VDD/VCCSYN.
This recommended power sequencing for the MSC8126 is different from the MSC8102. See Section 2.5.2 for start-up timing specifications.
The following sections discuss areas to consider when the MSC8126 device is designed into a system.
Use the following guidelines for start-up and power-down sequences:
Note:
External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time, including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes. This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the system during start-up.
During the power-up sequence, if VDD rises before VDDH (see Figure 6), current can pass from the VDD supply through the device ESD protection circuits to the VDDH supply. The ESD protection diode can allow this to occur when VDD exceeds VDDH by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:
••
Never allow VDD to exceed VDDH + 0.8V.
Design the VDDH supply to prevent reverse current flow by adding a minimum 10 Ω resistor to GND to limit the current. Such a design yields an initial VDDH level of VDD – 0.8 V before it is enabled.
After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V.
3.2Power Supply Design Considerations
When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines
described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8126 Design Checklist (AN3374 for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937) provides detailed design information. See Section 2.5.2 for start-up timing specifications.
Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved by using the following guidelines:
•
For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does not reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has better voltage recovery time than supplies with lower current ratings.
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Hardware Design Considerations
•
Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount at least one of the capacitors directly below the MSC8126 device.
Maximum IR drop of 15 mV at 1 A
1.2 V
Power supply
or
Voltage Regulator
Lmax = 2 cm
One 0.01 µF capacitorfor every 3 core supply pads.
MSC8122(Imin = 3 A)
+-
Bulk/Tantalum capacitorswith low ESR and ESL
Note: Use at least three capacitors.Each capacitor must be at least 150 μF.
High frequency capacitors(very low ESR and ESL)
Figure33. Core Power Supply Decoupling
Each VCC and VDD pin on the MSC8126 device should have a low-impedance path to the board power supply. Similarly, each GND pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the chip. The VCC power supply should have at least four 0.1 µF by-pass capacitors to ground located as closely as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes.
All output pins on the MSC8126 have fast rise and fall times. PCB trace interconnection length should be minimized to
minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.
Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins: VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to the one in Figure 34. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-µF capacitor should be closest to VCCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be kept short and direct. Provide an extremely low impedance path to the ground plane for GNDSYN. Bypass GNDSYN to VCCSYN by a 0.01-µF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of the PCB aligned with the depopulated void on the MSC8126 located in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13.
VDD
10Ω10nH
10 µF
0.01 µFVCCSYN
Figure34. VCCSYN Bypass
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Hardware Design Considerations
3.3
•••••••
Connectivity Guidelines
If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals can be disconnected.
When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either up or down, depending on design requirements.
HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the DCR[DSRFA] bit is set.
When the DSI is in -bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/ HDBE[1–3] and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].
When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3] must be pulled up.
When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.
When the DSI uses sliding window address mode (DCR[SLDWA] = 1), the external HA[11–13] signals must be connected (tied) to the correct voltage levels so that the host can perform the first access to the DCR. After reset, the DSI expects full address mode (DCR[SLDWA] = 0). The DCR address in the DSI memory map is 0x1BE000, which requires the following connections:—HA11 must be pulled high (1)—HA12 must be pulled high (1)—HA13 must be pulled low (0)
The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):—BG, DBG, and TS can be left unconnected.—EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.—BR must be pulled up.—EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.If there is an external bus master (BCR[EBM] = 1):—BR, BG, DBG, and TS must be pulled up.—EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus
functionality.
In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other modes, they must be pulled up.
The MSC8126 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).
If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the available clock modes.
IntheCLKIN synchronization mode, use the following connections:—Connect the oscillator output through a buffer to CLKIN.
—Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay path
between the clock buffer to the MSC8126 and the SDRAM is equal (that is, has a skew less than 100 ps).—Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.
In CLKOUT synchronization mode (for 1.2 V devices), CLKOUT is the main clock to SDRAM. Use the following connections:
—Connect the oscillator output through a buffer to CLKIN.
—Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the following
guidelines:
–The maximum delay between the slave and CLKOUT must not exceed 0.7 ns.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to
VDDH or GND, except for the following:
••
•
•Note:
••
•
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Hardware Design Considerations
–The maximum load on CLKOUT must not exceed 10 pF.–Use a zero-delay buffer with a jitter less than 0.3 ns.—All clock modes are valid in this clock scheme.
Note:
••
See the Clock chapter in the MSC8122 Reference Manual for details.
If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it should be pulled up.
The following signals: SWTE, DSISYNC, DSI, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are used to configure the MSC8126 and are sampled on the deassertion of the PORESET signal. Therefore, they should be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal.When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must be pulled up.
When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be connected externally to any signal line.
For details on configuration, see the MSC8126 User’s Guide and MSC8126 Reference Manual. For additional information, refer to the MSC8126 Design Checklist (AN2903).
••Note:
3.4External SDRAM Selection
The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to assure efficient data transfer across the bus. For example, for 166 MHz operation, you may have to use 183 or 200 MHz
SDRAM. Always perform a detailed timing analysis using the MSC8126 bus timing values and the manufacturer specifications for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by the SDRAM manufacturer.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Ordering Information
3.5Thermal Considerations
TJ = TA + (RθJA × PD)
Eqn.1
An estimation of the chip-junction temperature, TJ, in °C can be obtained from the following:
where
TA = ambient temperature near the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)PD = PINT + PI/O = power dissipation in the package (W)PINT = IDD × VDD = internal power dissipation (W)PI/O = power dissipated from device on output pins (W)
The power dissipation values for the MSC8126 are listed in Table2-3. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. The value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural convection) and well separated components. Based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case that is painted black. The MSC8126 device case surface is too shiny (low emissivity) to yield an accurate infrared temperature measurement. Use the following equation to determine TJ:
TJ = TT + (θJA × PD)
where
TT = thermocouple (or infrared) temperature on top of the package (°C)θJA = thermal characterization parameter (°C/W)PD = power dissipation in the package (W)
Note:
See MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601/D).
Eqn.2
4
Part
MSC8126Ordering Information
Package Type
Flip Chip Plastic Ball Grid Array (FC-PBGA)Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Core Voltage
1.2 VSpheres
Lead-freeLead-bearingLead-freeLead-bearing
Operating Temperature
–40° to 105°C0° to 90°C
Core
Frequency Order Number(MHz)
400500
MSC8126TVT00MSC8126TMP00MSC8126VT8000MSC8126MP8000
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Package Information
5Package Information
Notes:
1.All dimensions in millimeters.2.Dimensioning and tolerancing per ASME Y14.5M–1994.3.Features are symmetrical about the package center lines unless dimensioned otherwise.4.Maximum solder ball diameter measured parallel to Datum A.5.Datum A, the seating plane, is determined by the spherical crowns of the solder balls.6.Parallelism measurement shall exclude any effect of mark on top surface of package.7.Capacitors may not be present on all devices.8.Caution must be taken not to short capacitors or exposed metal capacitor pads on package top.9.FC CBGA (Ceramic) package code: 5238.
FC PBGA (Plastic) package code: 5263.10.Pin 1 indicator can be in the form of number 1 marking or an “L” shape marking.
Figure35. MSC8126 Mechanical Information, 431-pin FC-PBGA Package
6
••••
Product Documentation
MSC8126 Technical Data Sheet (MSC8126). Details the signals, AC/DC characteristics, clock signal characteristics, package and pinout, and electrical design considerations of the MSC8126 device.
MSC8126 Reference Manual (MSC8126RM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information.
Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8126 device.SC140 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program control, and instruction set.
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Revision History
7Revision History
Table31. Document Revision History
Table31 provides a revision history for this data sheet.
Revision
012
Date
May 2004Jun. 2004Sep 2004
Description
•Initial release.
•Updated timing number 32b.
•Updated DSI timing specifications.••••••••••••••••
New orderable parts added with other core voltage and temperature options.Updated thermal characteristics.
In Table 2-14, removed references to 30 pF.
Design guidelines and layout recommendations updated.Added 500 MHz core and 166 MHz bus speed options.Definitions of GPIO[27–28] updated.
Bus, TDM, and GPIO timing updated. I2C timing changed to GPIO timing.
GPIO[27–28] connections updated. MWBEn replaced with correct name HWBEn.Design guidelines update.
Package type changed to FC-PBGA for all frequencies.Low-voltage 300 MHz power changed to 1.1 V.HRESET and SRESET definitions updated.Undershoot and overshoot values added for VDDH.RMII timing updated.
Design guidelines updated and reorganized. Multiple AC timing specifications updated.
3Nov. 2004
4Jan. 2005
567
May 2005May 2005Jul. 2005Jul. 2005Sep. 2005
•Multiple AC timing specifications updated.•Multiple AC timing specifications updated.•••••••••••••••••
AC specification table layout modified.
ETHTX_EN type and TRST description updated.Package drawing updated.Clock specifications updated.Start-up sequence updated.
VDDH + 10% changed to VDDH + 8% in Figure 2-1.VDDH +20% changed to VDDH + 17% in Figure 2-1.
Reset timing updated to reflect actual values in Table 2-11.
Added new timings 17 and 18 for IRQ set time and pulse width in Table 2-13Converted to new data sheet format.
Added PLL supply current to Table 5 in Section 2.4.
Modified Figure 5 in Section 2.4 to make it clear that the time limits for undershoot referred to values below –0.3 V and not GND.
Added cross-references between Sections 2.5.2 and Section 3.1 and 3.2.Added power-sequence guidelines to Sections 2.5.2.
Added CLKIN jitter characteristic specifications to Table9.
Added additional guidelines to prevent reverse current to Section 3.1.
Added connectivity guidelines for DSI in sliding windows mode to Section 3.3.
10111213
Oct 2005Apr 2006Oct. 2006Dec. 2007
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Revision History
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
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Document Number: MSC8126
Rev. 1312/2007
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