FPGA-BASED SYSTEM POWER ESTIMATION APPARATUS AND M

专利名称：FPGA-BASED SYSTEM POWER ESTIMATION

APPARATUS AND METHOD

发明人：Yung-Chieh Lin,Shih-Che Lin,Chao-Hong

Chen,Liang-Chia Cheng

申请号：US15373466申请日：20161209

公开号：US20180120916A1公开日：20180503

专利附图：

摘要：A FPGA-based system power estimation apparatus and a method for estimatingthe power of a target intellectual property (IP) circuit are provided. The system power

estimation apparatus includes a FPGA and a power analysis circuit. The FPGA is configuredto accommodate the target IP circuit. The power analysis circuit is disposed into theFPGA. The power analysis circuit retrieves an internal operation-state signal of the targetIP circuit. The power analysis circuit examines the internal operation-state signal todetermine an operation state of the target IP circuit and uses a power model to convertthe operation state of the target IP circuit into at least one power value.

申请人：Industrial Technology Research Institute

地址：Hsinchu TW

国籍：TW

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