DRAM Memory Interface

专利名称：DRAM Memory Interface发明人：Cedric Bertholom申请号：US14343352申请日：20120906

公开号：US20140201436A1公开日：20140717

专利附图：

摘要：It is proposed a DRAM memory interface () for transmitting signals between amemory controller device () and a DRAM memory device (). The DRAM memory interfacecomprises: data lines () for transmitting data signals; one or more control line(s) fortransmitting control signals; one or more address line(s) for transmitting address signals;

for each line, a transmitter device () connected to a first end of the line and a receiverdevice () connected to a second end of the line; wherein: each line is a single ended linewherein a signal transmitted on the line is referenced to a first reference voltage line ();and —each line has an termination (Z, Z) on both the first and second ends of the line byconnecting a first impedance (Z) to the first end of the line and a second impedance (Z) tothe second end of the line.

申请人：Cedric Bertholom

地址：Vinay FR

国籍：FR

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