专利名称：Schmitt trigger inverter circuit发明人：斉藤 功申请号：JP2018007074申请日：20180119公开号：JP2019125995A公开日：20190725
专利附图：
摘要：The generation of a through current in a Schmitt trigger inverter circuit issuppressed. A Schmitt trigger inverter circuit SINVa includes a CMOS inverter CI whoseinput and output are connected to the input and output of the Schmitt trigger invertercircuit, respectively, and a first transistor MN3 whose gate is connected to the output of
the CMOS inverter. And a first current limiting element DEP1 connected in series with thefirst transistor. [Selection] Figure 1
申请人：富士電機株式会社
地址：神奈川県川崎市川崎区田辺新田１番１号
国籍：JP
代理人：奥山 尚一,有原 幸一,松島 鉄男,中村 綾子,森本 聡二,田中 祐,徳本 浩一
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