专利名称：Method and Apparatus for Verifying
Structural Correctness in Retimed Circuits
发明人：Mahesh A. Iyer申请号：US15790009申请日：20171022
公开号：US20180039724A1公开日：20180208
专利附图：
摘要：A method for designing a system on a target device includes performingregister retiming on an original design for the system to generate a retimed design.Whether the retimed design is structurally correct is verified by performing register
retiming on the retimed design.
申请人：Altera Corporation
地址：San Jose CA US
国籍：US
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