50 MHz, Precision, Low Distortion,
FEATURES
Bandwidth: 50 MHz @ 5 V Low noise: 4.5 nV/√Hz
Offset voltage: 100 μV typical, specified over entire common-mode range Slew rate: 41 V/μs
Rail-to-rail input and output swing Input bias current: 1 pA
Single-supply operation: 2.7 V to 5.5 V
Space-saving MSOP and SOIC_N packaging
APPLICATIONS
Optical communications
Laser source drivers/controllers Broadband communications High speed ADCs and DACs Microwave link interface Cell phone PA control Video line drivers Audio
GENERAL DESCRIPTION
The AD865x family consists of high precision, low noise, low distortion, rail-to-rail CMOS operational amplifiers that run from a single-supply voltage of 2.7 V to 5.5 V.
The AD865x family is made up of rail-to-rail input and output amplifiers with a gain bandwidth of 50 MHz and a typical voltage offset of 100 μV across common mode from a 5 V supply. It also features low noise—4.5 nV/√Hz.
The AD865x family can be used in communications
applications, such as cell phone transmission power control, fiber optic networking, wireless networking, and video line drivers.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Low Noise CMOS Amplifiers
AD8651/AD8652
PIN CONFIGURATIONS
NC18NCOUT A18V+–IN2AD86517V+–IN A2AD86527OUT B+IN3TOP VIEW6OUT+IN A3TOP VIEW6–IN B300V–4(Not to Scale)(Not to Scale)-5NC1V–45+IN B1030300-
1NC = NO CONNECT0330
Figure 1. 8-Lead MSOP (RM-8)
Figure 2. 8-Lead MSOP (RM-8)
NC18NCAD86518V+–IN27V+OUT A1+INAD86523TOP VIEW6OUT–IN A27OUT BV–44(Not to Scale)5NC+IN A3TOP VIEW6–IN B020-001-V–4(Not to Scale)5+IN B0133NC = NO CONNECT03030
Figure 3. 8-Lead SOIC_N (R-8)
Figure 4. 8-Lead SOIC_N (R-8)
The AD865x family features the newest generation of DigiTrim® in-package trimming. This new generation measures and corrects the offset over the entire input common-mode range, providing less distortion from VOS variation than is typical of other rail-to-rail amplifiers. Offset voltage and CMRR are both specified and guaranteed over the entire common-mode range as well as over the extended industrial temperature range. The AD865x family is offered in the narrow 8-lead SOIC package and the 8-lead MSOP package. The amplifiers are specified over the extended industrial temperature range (−40°C to +125°C).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
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AD8651/AD8652
TABLE OF CONTENTS
Features..............................................................................................1 Applications.......................................................................................1 Pin Configurations...........................................................................1 General Description.........................................................................1 Specifications.....................................................................................3 Electrical Characteristics.............................................................3 Absolute Maximum Ratings............................................................5 Thermal Resistance......................................................................5 ESD Caution..................................................................................5 Typical Performance Characteristics.............................................6 Applications.....................................................................................14 Theory of Operation..................................................................14 Rail-to-Rail Output Stage......................................................14 Rail-to-Rail Input Stage.........................................................14
Input Protection.....................................................................15 Overdrive Recovery...............................................................15 Layout, Grounding, and Bypassing Considerations..............15 Power Supply Bypassing........................................................15 Grounding...............................................................................15 Leakage Currents....................................................................15 Input Capacitance..................................................................16 Output Capacitance...............................................................16 Settling Time...........................................................................16 THD Readings vs. Common-Mode Voltage......................16 Driving a 16-Bit ADC............................................................17 Outline Dimensions.......................................................................18 Ordering Guide..........................................................................19
REVISION HISTORY
8/06—Rev. B. to Rev. C
Changes to Figure 1 to Figure 4......................................................1 Changes to Figure 7 and Figure 9...................................................6 Changes to Figure 23........................................................................9 Changes to Figure 53......................................................................14 Updated Outline Dimensions.......................................................18 Changes to Ordering Guide..........................................................19 9/04—Rev. A to Rev. B
Added AD8652....................................................................Universal Change to General Description.......................................................1 Changes to Electrical Characteristics.............................................3 Changes to Absolute Maximum Ratings........................................5 Change to Figure 23..........................................................................9 Change to Figure 26..........................................................................9 Change to Figure 36........................................................................11 Change to Figure 42........................................................................12 Change to Figure 49........................................................................13 Change to Figure 51........................................................................13 Inserted Figure 52............................................................................13 Change to Theory of Operation section.......................................14
Change to Input Protection section..............................................15 Changes to Ordering Guide...........................................................20 6/04—Rev. 0 to Rev. A
Change to Figure 18.............................................................................8 Change to Figure 21.............................................................................9 Change to Figure 29.............................................................................10 Change to Figure 30.............................................................................10 Change to Figure 43.............................................................................12 Change to Figure 44.............................................................................12 Change to Figure 47.............................................................................13 Change to Figure 57.............................................................................17 10/03 Revision 0: Initial Version
Rev. C | Page 2 of 20
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AD8651/AD8652
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V+ = 2.7 V, V– = 0 V, VCM = V+/2, TA = 25°C, unless otherwise specified. Table 1.
Parameter
Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS Offset Voltage VOS AD8651 0 V ≤ VCM ≤ 2.7 V 100 350 μV –40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 2.7 V 1.4 mV –40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V 1.6 mV
AD8652 0 V ≤ VCM ≤ 2.7 V 90 300 μV –40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V 0.4 1.3 mV Offset Voltage Drift TCVOS 4 μV/°C Input Bias Current IB 1 10 pA –40°C ≤ TA ≤ +125°C 600 pA Input Offset Current IOS 1 10 pA –40°C ≤ TA ≤ +85°C 30 pA –40°C ≤ TA ≤ +125°C 600 pA Input Voltage Range VCM –0.1 +2.8 V Common-Mode Rejection Ratio CMRR
+
AD8651 V = 2.7 V, –0.1 V < VCM < +2.8 V 75 95 dB –40°C ≤ TA ≤ +85°C, –0.1 V < VCM < +2.8 V 70 88 dB –40°C ≤ TA ≤ +125°C, –0.1 V < VCM < +2.8 V 65 85 dB
+
AD8652 V = 2.7 V, –0.1 V < VCM < +2.8 V 77 95 dB –40°C ≤ TA ≤ +125°C, –0.1 V < VCM < +2.8 V 73 90 dB Large Signal Voltage Gain AVORL = 1 kΩ, 200 mV < VO < 2.5 V 100 115 dB RL = 1 kΩ, 200 mV < VO < 2.5 V, TA = 85°C 100 114 dB RL = 1 kΩ, 200 mV < VO < 2.5 V, TA = 125°C 95 108 dB OUTPUT CHARACTERISTICS Output Voltage High VOHIL = 250 μA, –40°C ≤ TA ≤ +125°C 2.67 V Output Voltage Low VOLIL = 250 μA, –40°C ≤ TA ≤ +125°C 30 mV Short-Circuit Limit ISCSourcing 80 mA Sinking 80 mA Output Current IO 40 mA POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V, VCM = 0 V 76 94 dB –40°C ≤ TA ≤ +125°C 74 93 dB Supply Current ISY AD8651 IO = 0 9 12 mA –40°C ≤ TA ≤ +125°C 14.5 mA
AD8652 IO = 0 17.5 19.5 mA –40°C ≤ TA ≤ +125°C 22.5 mA INPUT CAPACITANCE CIN Differential 6 pF Common Mode 9 pF DYNAMIC PERFORMANCE Slew Rate SR G = 1, RL = 10 kΩ 41 V/μs Gain Bandwidth Product GBP G = 1 50 MHz Settling Time, 0.01% G = ±1, 2 V step 0.2 μs
+
Overload Recovery Time VIN × G = 1.48 V 0.1 μs Total Harmonic Distortion + Noise THD + N G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p 0.0006 % NOISE PERFORMANCE Voltage Noise Density enf = 10 kHz 5 nV/√Hz f = 100 kHz 4.5 nV/√Hz Current Noise Density inf = 10 kHz 4 fA/√Hz
Rev. C | Page 3 of 20
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AD8651/AD8652
V+ = 5 V, V– = 0 V, VCM = V+/2, TA = 25°C, unless otherwise specified. Table 2.
Parameter Symbol Conditions
Min Typ Max Unit
INPUT CHARACTERISTICS Offset Voltage VOS AD8651 0 V ≤ VCM ≤ 5 V 100 350 μV –40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 5 V 1.4 mV –40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V 1.7 mV
AD8652 0 V ≤ VCM ≤ 5 V 90 300 μV –40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V 0.4 1.4 mV Offset Voltage Drift TCVOS 4 μV/°C Input Bias Current IB 1 10 pA –40°C ≤ TA ≤ +85°C 30 pA –40°C ≤ TA ≤ +125°C 600 pA Input Offset Current IOS 1 10 pA –40°C ≤ TA ≤ +85°C 30 pA –40°C ≤ TA ≤ +125°C 600 pA Input Voltage Range VCM –0.1 +5.1 V Common-Mode Rejection Ratio CMRR AD8651 0.1 V < VCM < 5.1 V 80 95 dB –40°C ≤ TA ≤ +85°C, 0.1 V < VCM < 5.1 V 75 94 dB –40°C ≤ TA ≤ +125°C, 0.1 V < VCM < 5.1 V 70 90 dB
AD8652 0.1 V < VCM < 5.1 V 84 100 dB –40°C ≤ TA ≤ +125°C, 0.1 V < VCM < 5.1 V 76 95 dB Large Signal Voltage Gain AVORL = 1 kΩ, 200 mV < VO < 4.8 V 100 115 dB RL = 1 kΩ, 200 mV < VO < 4.8 V, TA = 85°C 98 114 dB RL = 1 kΩ, 200 mV < VO < 4.8 V, TA = 125°C 95 111 dB OUTPUT CHARACTERISTICS Output Voltage High VOHIL = 250 μA, –40°C ≤ TA ≤ +125°C 4.97 V Output Voltage Low VOLIL = 250 μA, –40°C ≤ TA ≤ +125°C 30 mV Short-Circuit Limit ISCSourcing 80 mA Sinking 80 mA Output Current IO 40 mA POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V, VCM = 0 V 76 94 dB –40°C ≤ TA ≤ +125°C 74 93 dB Supply Current ISY AD8651 IO = 0 9.5 14.0 mA –40°C ≤ TA ≤ +125°C 15 mA
AD8652 IO = 0 17.5 20.0 mA –40°C ≤ TA ≤ +125°C 23.5 mA INPUT CAPACITANCE CIN Differential 6 pF Common Mode 9 pF DYNAMIC PERFORMANCE Slew Rate SR G = 1, RL = 10 kΩ 41 V/μs Gain Bandwidth Product GBP G = 1 50 MHz Settling Time, 0.01% G = ±1, 2 V step 0.2 μs
+
Overload Recovery Time VIN × G = 1.2 V 0.1 μs Total Harmonic Distortion + Noise THD + N G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p 0.0006 % NOISE PERFORMANCE Voltage Noise Density enf = 10 kHz 5 nV/√Hz f = 100 kHz 4.5 nV/√Hz Current Noise Density inf = 10 kHz 4 fA/√Hz
Rev. C | Page 4 of 20
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AD8651/AD8652
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 3.
Parameter Rating JA is specified for the worst-case conditions, that is, a device
Supply Voltage 6.0 V
soldered in a circuit board for surface-mount packages.
Input Voltage GND to VS + 0.3 V
Table 4. Thermal Resistance Differential Input Voltage ±6.0 V
Package Type θJAθJCUnit Output Short-Circuit Duration to GND Indefinite
8-Lead MSOP (RM) 210 45 °C/W Electrostatic Discharge (HBM) 4000 V
8-Lead SOIC_N (R) 158 43 °C/W Storage Temperature Range
RM, R Package −65°C to +150°C Operating Temperature Range −40°C to +125°C Junction Temperature Range RM, R Package −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C
THERMAL RESISTANCE
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. C | Page 5 of 20
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AD8651/AD8652
TYPICAL PERFORMANCE CHARACTERISTICS
60VS = ±2.5VVCM = 0V50NUMBER OFAMPLIFIERS80100VS = 5V40VOS (µV)603040202010040–80–4080120160–200–160–12020003301-00501234COMMON-MODE VOLTAGE (V)5603301-00800–20VOS (µV)
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
500VS = ±2.5V400
Figure 5. Input Offset Voltage Distribution
300VS = ±2.5VVCM = 0V200100INPUT BIAS CURRENT (pA)03301-006300VOS (µV)0200–100–200100050TEMPERATURE (°C)10015002040
6080100TEMPERATURE (°C)12014003301-00903301-010–300–500
Figure 6. Input Offset Voltage vs. Temperature
60VS=±2.5VVCM=0VTA:–40°CTO+125°C
Figure 9. Input Bias Current vs. Temperature
10508NUMBER OFAMPLIFIERS40SUPPLY CURRENT (mA)01234567TCVOS(µV/°C)89101103301-0076304201020001234SUPPLY VOLTAGE (V)56
Figure 7. TCVOS Distribution Figure 10. Supply Current vs. Supply Voltage
Rev. C | Page 6 of 20
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12VS = ±2.5V11AD8651/AD8652
2.50VS = 5VIL = 250µA2.00OUTPUT SWING LOW (mV)03301-011SUPPLY CURRENT (mA)101.5091.00870.50050TEMPERATURE (°C)1001500
50TEMPERATURE (°C)10015003301-01403301-01503301-0166–500–50
Figure 11. Supply Current vs. Temperature
500VS=±2.5V40080100
Figure 14. Output Voltage Swing Low vs. Temperature
VS = ±2.5V(VSY – VOUT) (mV)VOH200VOL100CMRR (dB)8010003301-01230060402000204060CURRENTLOAD(mA)0101001k
10k100kFREQUENCY (Hz)1M10M
Figure 12. Output Voltage to Supply Rail vs. Load Current
4.9974.996VS = 5VIL = 250µA105110Figure 15. CMRR vs. Frequency
VS = ±2.5VOUTPUT SWING HIGH (V)4.9954.9944.9934.9924.9914.990–50CMRR (dB)050TEMPERATURE (°C)10015003301-0131009590–500
50TEMPERATURE (°C)100150
Figure 13. Output Voltage Swing High vs. Temperature
Figure 16. CMRR vs. Temperature
Rev. C | Page 7 of 20
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AD8651/AD8652
100100VS = ±2.5V9491VOLTAGE NOISE DENSITY (nV/√Hz)97CMRR (dB)108885050TEMPERATURE (°C)100150100
1kFREQUENCY (Hz)10k100k03301-02003301-02103301-02203301-01782–50110
Figure 17. CMRR vs. Temperature
100VS = ±2.5V80+PSRR60–PSRR4080Figure 20. Voltage Noise Density vs. Frequency
VS = ±2.5VCURRENT NOISE DENSITY (fA/√Hz)03301-01860PSRR (dB)40202001101001k10k100kFREQUENCY (Hz)1M10M100M01001kFREQUENCY (Hz)10k100k
Figure 18. PSRR vs. Frequency
100VS = ±2.5VFigure 21. Current Noise Density vs. Frequency
VS = ±2.5VVIN= 6.4VVIN95VOLTAGE (1V/DIV)VOUT0PSRR (dB)9085050TEMPERATURE (°C)10015003301-01980–50
TIME (200µs/DIV)
Figure 19. PSRR vs. Temperature Figure 22. No Phase Reversal
Rev. C | Page 8 of 20
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140VS = ±2.5V12040AD8651/AD8652
060VS = ±2.5VRL = 1MΩCL = 47pFG = 100806040200–135–90CLOSED-LOOP GAIN (dB)100–45OPEN-LOOP GAIN (dB)PHASE (Degrees)20G = 100G = 1–2003301-0231001k10k100k1MFREQUENCY (Hz)10M100M50k
500k5MFREQUENCY (Hz)50M300M03301-02603301-02703301-028–2010–180–405k
Figure 23. Open-Loop Gain and Phase vs. Frequency
117VS = ±2.5VRL= 1kΩ6Figure 26. Closed-Loop Gain vs. Frequency
MAXIMUM OUTPUT SWING (V)1165VS = 5V4OPEN-LOOP GAIN (dB)1153VS = 2.7V2114113103301-024112–50050TEMPERATURE (°C)1001500100k1M
10MFREQUENCY (Hz)100M
Figure 24. Open-Loop Gain vs. Temperature
140VS=±2.5V13012011010090807003301-025Figure 27. Maximum Output Swing vs. Frequency
VS = ±2.5VCL = 47pFAV= 1IL=250µAIL=2.5mAOPEN-LOOPGAIN(dB)60010015020050OUTPUTVOLTAGESWINGFROMTHERAILS(mV)250VOLTAGE (1V/DIV)IL=4.2mA
TIME (100µs/DIV)
Figure 25. Open-Loop Gain vs. Output Voltage Swing Figure 28. Large Signal Response
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AD8651/AD8652
VS = ±2.5VVIN= 200mVAV = 1VS = ±2.5VVIN= 200mVGAIN = –15OUTPUT0VVOLTAGE (100mV/DIV)–2.5V200mVINPUT0V03301-029TIME (10µs/DIV)
TIME (200ns/DIV)03301-032
Figure 29. Small Signal Response
30VS = ±2.5VVIN = 200mVAV = 1OUTPUT IMPEDANCE (Ω)3040Figure 32. Positive Overload Recovery Time
VS = ±2.5VSMALL SIGNAL OVERSHOOT (%)2520–OS15+OS1020GAIN = 10GAIN = 1GAIN = 100010
105010203040CAPACITANCE (pF)506070100
1k
FREQUENCY (Hz)
10k100k
03301-03303301-03403301-0300
Figure 30. Small Signal Overshoot vs. Load Capacitance
2.5VVS = ±2.5VVIN= 200mVGAIN = –1560Figure 33. Output Impedance vs. Frequency
VS = ±1.35VVCM = 0V50NUMBER OFAMPLIFIERS03301-0310V40300V–200mV20100040–80–4080120160–200–160TIME (200ns/DIV)
–120
Figure 31. Negative Overload Recovery Time
VOS (µV)200
Figure 34. Input Offset Voltage Distribution
Rev. C | Page 10 of 20
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300VS = ±1.35VVCM = 0V200400500AD8651/AD8652
VS=±1.35V(VSY – VOUT) (mV)100300VOH200VOL100VOS (µV)0–100–200050TEMPERATURE (°C)100150020
4060CURRENTLOAD(mA)8010003301-03803301-03903301-04003301-035–300–500
Figure 35. Input Offset Voltage vs. Temperature
80VS = 2.7V2.69660
Figure 38. Output Voltage to Supply Rail vs. Load Current
2.697VS = 2.7VIL = 250µAINPUT OFFSET VOLTAGE (µV)40OUTPUT SWING HIGH (V)012INPUT COMMON-MODE VOLTAGE (V)03301-0362.6952.6942.6932.6922.691200–2032.690–500
50TEMPERATURE (°C)100150
Figure 36. Input Offset Voltage vs. Common-Mode Voltage
11VS = ±1.35V102.503.00
Figure 39. Output Voltage Swing High vs. Temperature
VS = 2.7VIL = 250µAOUTPUT SWING LOW (mV)050TEMPERATURE (°C)10015003301-037SUPPLY CURRENT (mA)2.0091.5081.0070.506–500–500
50TEMPERATURE (°C)100150
Figure 37. Supply Current vs. Temperature
Figure 40. Output Voltage Swing Low vs. Temperature
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AD8651/AD8652
VS = ±1.35VAV= 130VS = ±1.35VVIN = 200mVSMALL SIGNAL OVERSHOOT (%)25VOLTAGE (1V/DIV)2015–OS10+OS503301-04101020TIME (200µs/DIV)
3040CAPACITANCE (pF)50607003301-04403301-04503301-0460
Figure 41. No Phase Reversal
VS = ±1.35VCL= 47pFAV = 1Figure 44. Small Signal Overshoot vs. Load Capacitance
VS = ±1.35VVIN= 200mVGAIN = –101.35VVOLTAGE (500mV/DIV)0V0V–200mV03301-042TIME (100µs/DIV)
TIME (200ns/DIV)
Figure 42. Large Signal Response
VS = ±1.35VVIN= 200mVCL = 47pFAV = 1Figure 45. Negative Overload Recovery Time
VS = ±1.35VVIN= 200mVGAIN = –100VVOLTAGE (100mV/DIV)–1.35V200mV0V03301-043TIME (10µs/DIV)
TIME (200ns/DIV)
Figure 43. Small Signal Response Figure 46. Positive Overload Recovery Time
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100VS = ±1.35V80118120AD8651/AD8652
VS = ±1.35VRL= 1kΩ116CMRR (dB)60AVO (dB)03301-04711440112201101001k10k100kFREQUENCY (Hz)1M10M0
50TEMPERATURE (°C)10015003301-050010108–50
Figure 47. CMRR vs. Frequency
100VS = ±1.35V804060Figure 50. Open-Loop Gain vs. Temperature
VS = ±1.35VRL = 1MΩCL = 47pFG = 100CLOSED-LOOP GAIN (dB)+PSRR60–PSRR20PSRR (dB)G = 10400G = 120–2003301-0481101001k10kFREQUENCY (Hz)100k1M10M50k
500k5MFREQUENCY (Hz)50M300M03301-0510–405k
Figure 48. PSRR vs. Frequency
140VS =±1.35V120100–450
Figure 51. Closed-Loop Gain vs. Frequency
0–20+2.5VVIN–40–60–80–100–120–180R110kΩV–VOUTV+R2100ΩV+V––2.5VCHANNEL SEPARATION (dB)OPEN-LOOPGAIN(dB)28mV p-p806040200–135–90PHASE(Degrees)03301-0491001k10k100k1MFREQUENCY (Hz)10M100M1k
10k100kFREQUENCY (Hz)1M10M03301-052–2010–140100VS = ±2.5V
Figure 49. Open-Loop Gain and Phase vs. Frequency
Figure 52. Channel Separation vs. Frequency.
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AD8651/AD8652
APPLICATIONS
THEORY OF OPERATION
The AD865x family consists of voltage feedback, rail-to-rail input and output precision CMOS amplifiers that operate from 2.7 V to 5.5 V of power supply voltage. These amplifiers use Analog Devices, Inc. DigiTrim technology to achieve a higher degree of precision than is available from most CMOS
amplifiers. DigiTrim technology, used in a number of Analog Devices amplifiers, is a method of trimming the offset voltage of the amplifier after it has been assembled. The advantage of post-package trimming is that it corrects any offset voltages caused by the mechanical stresses of assembly.
The AD865x family is available in standard op amp pinouts, making DigiTrim completely transparent to the user. The input stage of the amplifiers is a true rail-to-rail architecture, allowing the input common-mode voltage range of the op amp to extend to both positive and negative supply rails. The open-loop gain of the AD865x with a load of 1 kΩ is typically 115 dB. The AD865x can be used in any precision op amp application. The amplifiers do not exhibit phase reversal for common-mode voltages within the power supply. With voltage noise of
4.5 nV/√Hz and –105 dB distortion for 10 kHz, 2 V p-p signals, the AD865x is a great choice for high resolution data
acquisition systems. Their low noise, sub-pA input bias current, precision offset, and high speed make them superb preamps for fast photodiode applications. The speed and output drive capabilities of the AD865x also make the amplifiers useful in video applications.
The NMOS and PMOS input stages are separately trimmed using DigiTrim to minimize the offset voltage in both differen-tial pairs. Both NMOS and PMOS input differential pairs are active in a 500 mV transition region when the input common-mode voltage is approximately 1.5 V below the positive supply voltage. A special design technique improves the input offset voltage in the transition region that traditionally exhibits a slight VOS variation. As a result, the common-mode rejection ratio is improved within this transition band. Compared to the Burr Brown OPA350 amplifier, shown in Figure 53, the
AD865x, shown in Figure 54, exhibits much lower offset voltage shift across the entire input common-mode range, including the transition region.
600400200VOS (µV)0–200–40001234COMMON-MODE VOLTAGE (V)5603301-05303301-061–600
Figure 53. Input Offset Distribution over Common-Mode
Voltage for the OPA350
Rail-to-Rail Output Stage
The voltage swing of the output stage is rail-to-rail and is achieved by using an NMOS and PMOS transistor pair con-nected in a common source configuration. The maximum output voltage swing is proportional to the output current, and larger currents will limit how close the output voltage can get to the proximity of the output voltage to the supply rail. This is a characteristic of all rail-to-rail output amplifiers. With 40 mA of output current, the output voltage can reach within 5 mV of the positive and negative rails. At light loads of >100 kΩ, the output swings within ~1 mV of the supplies.
600400200VOS (µV)0–200Rail-to-Rail Input Stage
The input common-mode voltage range of the AD865x extends to both positive and negative supply voltages. This maximizes the usable voltage range of the amplifier, an important feature for single-supply and low voltage applications. This rail-to-rail input range is achieved by using two input differential pairs, one NMOS and one PMOS, placed in parallel. The NMOS pair is active at the upper end of the common-mode voltage range, and the PMOS pair is active at the lower end of the common-mode range.
–400–60001234COMMON-MODE VOLTAGE (V)56Figure 54. Input Offset Distribution over Common-Mode
Input Protection for the AD865x
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AD8651/AD8652
Bypassing schemes are designed to minimize the supply impedance at all frequencies with a parallel combination of capacitors of 0.1 μF and 4.7 μF. Chip capacitors of 0.1 μF (X7R or NPO) are critical and should be as close as possible to the amplifier package. The 4.7 μF tantalum capacitor is less critical for high frequency bypassing, and, in most cases, only one is needed per board at the supply inputs.
Input Protection
As with any semiconductor device, if a condition exists for the input voltage to exceed the power supply, the device input
overvoltage characteristic must be considered. The inputs of the AD865x family are protected with ESD diodes to either power supply. Excess input voltage energizes internal PN junctions in the AD865x, allowing current to flow from the input to the supplies. This results in an input stage with picoamps of input current that can withstand up to 4000 V ESD events (human body model) with no degradation.
Excessive power dissipation through the protection devices
destroys or degrades the performance of any amplifier. Differential voltages greater than 7 V result in an input current of approximately (| VCC – VEE | – 0.7 V)/RI, where RI is the resistance in series with the inputs. For input voltages beyond the positive supply, the input current is approximately (VIN – VCC – 0.7)/RI. For input voltages beyond the negative supply, the input current is about (VIN – VEE + 0.7)/RI. If the inputs of the amplifier sustain
differential voltages greater than 7 V or input voltages beyond the amplifier power supply, limit the input current to 10 mA by using an appropriately sized input resistor (RI), as shown in Figure 55.
RI>(|VCC–VEE|–0.7V)30mARI>RI>(VIN–VEE–0.7V)30mA(VIN–VEE+0.7V)30mAFORVINBEYONDSUPPLYVOLTAGES03301-054Grounding
A ground plane layer is important for densely packed PC
boards to spread the current-minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the high frequency impedance of the path. High speed currents in an inductive ground return create an unwanted voltage noise. The length of the high frequency bypass capacitor leads is critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Place the ground leads of the bypass capacitors at the same physical location. Because load currents also flow from the supplies, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, intended to be effective at lower frequencies, the current return path distance is less critical.
FORLARGE|VCC–VEE|+AD865x–VIN+–RI+VOLeakage Currents
Figure 55. Input Protection Method
Overdrive Recovery
Overdrive recovery is defined as the time it takes for the output of an amplifier to come off the supply rail after an overload signal is initiated. This is usually tested by placing the amplifier in a closed-loop gain of 15 with an input square wave of 200 mV p-p while the amplifier is powered from either 5 V or 3 V. The AD865x family has excellent recovery time from overload conditions (see Figure 31 and Figure 32). The output recovers from the positive supply rail within 200 ns at all supply voltages. Recovery from the negative rail is within 100 ns at 5 V supply.
Poor PC board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the AD865x family. Any voltage differential between the inputs and nearby traces sets up leakage currents through the PC board insulator, for example 1 V/100 G = 10 pA. Similarly, any contaminants on the board can create significant leakage (skin oils are a common problem).
To significantly reduce leakages, put a guard ring (shield) around the inputs and the input leads that are driven to the same voltage potential as the inputs. This ensures that there is no voltage potential between the inputs and the surrounding area to set up any leakage currents. To be effective, the guard ring must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above and below, using a multilayer board.
Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring helps to reduce the absorption. Also, low absorption materials, such as Teflon® or ceramic, may be necessary in some instances.
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
Power Supply Bypassing
Power supply pins can act as inputs for noise, so care must be taken that a noise-free, stable dc voltage is applied. The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering most of the noise.
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AD8651/AD8652
Input Capacitance
Along with bypassing and grounding, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few picofarads of capacitance reduces the input impedance at high frequencies, which in turn increases the amplifier gain, causing peaking in the frequency response or oscillations. With the AD865x, additional input damping is required for stability with capacitive loads greater than 47 pF with direct input to output feedback (see the Output Capacitance section).
•
Another way to stabilize an op amp driving a large capacitive load is to use a snubber network, as shown in Figure 57. Because there is not any isolation resistor in the signal path, this method has the significant advantage of not reducing the output swing. The exact values of RS and CS are derived experimentally. In Figure 57, an optimum RS and CS combination for a capacitive load drive ranging from 50 pF to 1 nF was chosen. For this, RS = 3 Ω and CS = 10 nF were chosen.
V+Output Capacitance
When using high speed amplifiers, it is important to consider the effects of the capacitive loading on amplifier stability. Capacitive loading interacts with the output impedance of the amplifier, causing reduction of the BW as well as peaking and ringing of the frequency response. To reduce the effects of the capacitive loading and allow higher capacitive loads, there are two commonly used methods. •
As shown in Figure 56, place a small value resistor (RS) in series with the output to isolate the load capacitor from the amplifier output. Heavy capacitive loads can reduce the phase margin of an amplifier and cause the amplifier response to peak or become unstable. The AD865x is able to drive up to 47 pF in a unity gain buffer configuration without oscillation or external compensation. However, if an application requires a higher capacitive load drive when the AD865x is in unity gain, the use of external isolation networks can be used. The effect produced by this resistor is to isolate the op amp output from the capacitive load. The required amount of series resistance has been
tabulated in Table 5 for different capacitive loads. While this technique improves the overall capacitive load drive for the amplifier, its biggest drawback is that it reduces the output swing of the overall circuit.
VCC3VIN2U1+V+VOUTRS03301-056AD865x––V200mVV–CSCLRL
Figure 57. Snubber Network
Settling Time
The settling time of an amplifier is defined as the time it takes for the output to respond to a step change of input and enter and remain within a defined error band, as measured relative to the 50% point of the input pulse. This parameter is especially important in measurements and control circuits where amplifi-ers are used to buffer A/D inputs or DAC outputs. The design of the AD865x family combines a high slew rate and a wide gain bandwidth product to produce an amplifier with very fast settling time. The AD865x is configured in the noninverting gain of 1 with a 2 V p-p step applied to its input. The AD865x family has a settling time of about 130 ns to 0.01% (2 mV). The output is monitored with a 10×, 10 M, 11.2 pF scope probe.
THD Readings vs. Common-Mode Voltage
Total harmonic distortion of the AD865x family is well below 0.0004% with any load down to 600 Ω. The distortion is a function of the circuit configuration, the voltage applied, and the layout, in addition to other factors. The AD865x family outperforms its competitor for distortion, especially at frequencies below 20 kHz, as shown in Figure 58.
0.10.05VSY = +3.5V/–1.5VVOUT = 2.0V p-p+V+AD865x––VRSVOUTCL0RL03301-05500.020Figure 56. Driving Large Capacitive Loads
THD + NOISE (%)
0.010.0050.0020.001OPA350
Table 5. Optimum Values for Driving Large Capacitive Loads
CL 100 pF 500 pF 1.0 nF
RS 50 Ω 35 Ω 25 Ω
0.00050.00020.00012050100AD865103301-057
Rev. C | Page 16 of 20
5001k2kFREQUENCY (Hz)5k20k
Figure 58. Total Harmonic Distortion
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+3.5V5VAD8651/AD8652
+10kΩU1AD865x–VIN2Vp-p–1.5V600Ω47pFVOUT1µF03301-0583+–10kΩ2VIN0VTO5VfIN=45kHz1kΩV+V–AD865x33ΩIN2.7nFVCCAD7685Figure 59. THD + N Test Circuit
1kΩ03301-060
Driving a 16-Bit ADC
The AD865x family is an excellent choice for driving high speed, high precision ADCs. The driver amplifier for this type of application needs low THD + N as well as quick settling time. Figure 61 shows a complete single-supply data acquisition solution. The AD865x family drives the AD7685, a 250 kSPS, 16-bit data converter.1
The AD865x is configured in an inverting gain of 1 with a 5 V single supply. Input of 45 kHz is applied, and the ADC samples at 250 kSPS. The results of this solution are listed in Table 6. The advantage of this circuit is that the amplifier and ADC can be powered with the same power supply. For the case of a noninverting gain of 1, the input common-mode voltage encompasses both supplies.
1
Figure 61. AD865x Driving a 16-Bit ADC
Table 6. Data Acquisition Solution of Figure 60
Parameter Reading (dB) THD + N 105.2
SFDR 106.6 2nd Harmonics 107.7 3rd Harmonics 113.6
For more information about the AD7685 data converter, go to
http://www.analog.com/Analog_Root/productPage/productHome/0%2C2121%2CAD7685%2C00.html
0–20fSAMPLE = 250kSPSfIN = 45kHzINPUT RANGE = 0VTO 5VAMPLITUDE (dB of Full Scale)–40–60–80–100–120–140–160
01020304050607080FREQUENCY (kHz)9010011012003301-059
Figure 60. Frequency Response of AD865x Driving a 16-Bit ADC
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AD8651/AD8652
OUTLINE DIMENSIONS
3.203.002.803.203.002.808515.154.904.654PIN 10.65 BSC0.950.850.750.150.000.380.22SEATINGPLANE1.10 MAX8°0°0.800.600.400.230.08COPLANARITY0.10COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 62. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00(0.1968)4.80(0.1890)4.00 (0.1574)3.80 (0.1497)81546.20 (0.2440)5.80 (0.2284)1.27 (0.0500)BSC0.25 (0.0098)0.10 (0.0040)COPLANARITY0.10SEATINGPLANE1.75 (0.0688)1.35 (0.0532)0.50 (0.0196)0.25 (0.0099)8°0°0.25 (0.0098)0.17 (0.0067)1.27 (0.0500)0.40 (0.0157)45°0.51 (0.0201)0.31 (0.0122)COMPLIANTTO JEDEC STANDARDS MS-012-AACONTROLLING DIMENSIONSARE IN MILLIMETERS; INCH DIMENSIONS(INPARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLYANDARE NOTAPPROPRIATE FOR USE IN DESIGN.060506-A
Figure 63. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. C | Page 18 of 20
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AD8651/AD8652
Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C
Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N
Package Option RM-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 R-8 R-8 R-8
Branding BEA BEA BEA# BEA# A05 A05
ORDERING GUIDE
Model
AD8651ARM-REEL AD8651ARM-R2 AD8651ARMZ-REEL1 AD8651ARMZ-R21 AD8651AR
AD8651AR-REEL AD8651AR-REEL7 AD8651ARZ1
AD8651ARZ-REEL1 AD8651ARZ-REEL71 AD8652ARMZ-R21 AD8652ARMZ-REEL1 AD8652ARZ1
AD8652ARZ-REEL1 AD8652ARZ-REEL71
1
Z = Pb-free part; # denotes lead-free product may be top or bottom marked.
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AD8651/AD8652
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03301-0-8/06(C)
Rev. C | Page 20 of 20
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