74ls160芯片同步十进制计数器(直接清零)

本电路是由4 个主从触发器和用作除2计数器与计数周期长度为除5的3位2进制计数器所用的附加选通所组成。有选通的零复位和置9输入。为了利用本计数器的最大计数长度〔十进制〕，可将B输入同QA 输出连接，输入计数脉冲可加到输入A上，此时输出就如相应的功能表上所要求的那样。LS90可以获得对称的十分频计数，方法是将QD 输出接到A输入端，并把输入计数脉冲加到B输入端，在QA输出端处产生对称的十分频方波。

74160引脚图

交流波形图：

图1 时钟到输出延迟计数 图2 主复位输出延迟，主复位 时钟频率，脉冲宽度 脉冲宽度，和主复位恢

复时间

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状态图

VHDL十进制计数器

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity count10 is

port (clk:in std_logic;

f:buffer integer range 0 to 15; cout:out std_logic); end;

architecture aa of count10 is begin

process(clk) begin

if falling_edge(clk) then if f=9 then f<=0;

cout<='1'; else f<=f+1; end if; else

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null; end if;

end process; end;

十进制计数器VHDL

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --**************实体*****************

entity shijinzhi is

port(

clk: in std_logic;

reset: in std_logic;

s : out std_logic_vector(5 downto 0);

out1: out std_logic_vector(7 downto 0)

);

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end shijinzhi;

--*****************结构体***********************

architecture one of shijinzhi is signal clk_500 : std_logic;--扫描时钟 signal clk_1 : std_logic;--1s时钟

begin

--*************500Hz分频程序********************

process(clk)

variable t1 : integer range 0 to 200; variable t2 : integer range 0 to 250;

begin

if clk'event and clk='1' then

if t1=200 then

t1:=0;

if t2=250 then

t2:=0;

clk_500<=not clk_500;

else t2:=t2+1; end if; else t1:=t1+1;

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end if; end if; end process;

--***********1Hz分频程序和扫描信号产生********************

process(clk_500)

variable t3 : integer range 0 to 250;

begin

if clk_500'event and clk_500='1' then

if t3=250 then

t3:=0;

clk_1<=not clk_1;

else t3:=t3+1; end if;

end if; end process;

--****************************************

process(clk_1,reset)

variable count1:integer range 0 to 9;

begin

if reset='0' then count1:=0;

elsif clk_1'event and clk_1='1' then

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if count1=9 then

count1:=0;

else

count1:=count1+1;

end if; end if;

if clk_500='1' then

case count1 is

WHEN 0 =>s<=\"111110\";out1<=\"10111111\"; WHEN 1 =>s<=\"111110\";out1<=\"10000110\"; WHEN 2 =>s<=\"111110\";out1<=\"11011011\"; WHEN 3 =>s<=\"111110\";out1<=\"11001111\"; WHEN 4 =>s<=\"111110\";out1<=\"11100110\"; WHEN 5 =>s<=\"111110\";out1<=\"11101101\"; WHEN 6 =>s<=\"111110\";out1<=\"11111101\"; WHEN 7 =>s<=\"111110\";out1<=\"10000111\"; WHEN 8 =>s<=\"111110\";out1<=\"11111111\";

WHEN 9 =>s<=\"111110\";out1<=\"11101111\";

when others=>out1<=\"00000000\";

end case; end if;

end process;

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end one;

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