MEMORY存储芯片P87C52SFBB中文规格书

Enhanced UARTThe UART operates in all of the usual modes that are described inthe first section of Data Handbook IC20, 80C51-Based 8-BitMicrocontrollers. In addition the UART can perform framing errordetect by looking for missing stop bits, and automatic addressrecognition. The UART also fully supports multiprocessorcommunication as does the standard 80C51 UART.When used for framing error detect the UART looks for missing stopbits in the communication. A missing bit will set the FE bit in theSCON register. The FE bit shares the SCON.7 bit with SM0 and thefunction of SCON.7 is determined by PCON.6 (SMOD0) (seeFigure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7functions as SM0 when SMOD0 is cleared. When used as FESCON.7 can only be cleared by software. Refer to Figure 8.Automatic Address RecognitionAutomatic Address Recognition is a feature which allows the UARTto recognize certain addresses in the serial bit stream by usinghardware to make the comparisons. This feature saves a great dealof software overhead by eliminating the need for the software toexamine every serial address which passes by the serial port. Thisfeature is enabled by setting the SM2 bit in SCON. In the 9 bit UARTmodes, mode 2 and mode 3, the Receive Interrupt flag (RI) will beautomatically set when the received byte contains either the “Given”address or the “Broadcast” address. The 9 bit mode requires thatthe 9th information bit is a 1 to indicate that the received informationis an address and not data. Automatic address recognition is shownin Figure 9.The 8 bit mode is called Mode 1. In this mode the RI flag will be setif SM2 is enabled and the information received has a valid stop bitfollowing the 8 address bits and the information is either a Given orBroadcast address.Mode 0 is the Shift Register mode and SM2 is ignored.Using the Automatic Address Recognition feature allows a master toselectively communicate with one or more slaves by invoking theGiven slave address or addresses. All of the slaves may becontacted by using the Broadcast address. Two special FunctionRegisters are used to define the slave’s address, SADDR, and theaddress mask, SADEN. SADEN is used to define which bits in theSADDR are to b used and which bits are “don’t care”. The SADENmask can be logically ANDed with the SADDR to create the “Given”address which the master will use for addressing each of the slaves.Use of the Given address allows multiple slaves to be recognizedwhile excluding others. The following examples will help to show theversatility of this scheme:Slave 0SADDR= 1100 0000SADEN= 1111 1101Given=110000X01999 Apr 01Slave 1SADDR= 1100 0000SADEN= 1111 1110Given=1100000XIn the above example SADDR is the same and the SADEN data isused to differentiate between the two slaves. Slave 0 requires a 0 inbit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 isignored. A unique address for Slave 0 would be 1100 0010 sinceslave 1 requires a 0 in bit 1. A unique address for slave 1 would be1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can beselected at the same time by an address which has bit 0 = 0 (forslave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressedwith 1100 0000.In a more complex system the following could be used to selectslaves 1 and 2 while excluding slave 0:Slave 0SADDR= 1100 0000SADEN= 1111 1001Given=11000XX0Slave 1SADDR= 1110 0000SADEN= 1111 1010Given=11100X0XSlave 2SADDR= 1110 0000SADEN= 1111 1100Given=111000XXIn the above example the differentiation among the 3 slaves is in thelower 3 address bits. Slave 0 requires that bit 0 = 0 and it can beuniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 andit can be uniquely addressed by 1110 and 0101. Slave 2 requiresthat bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0and 1 and exclude Slave 2 use address 1110 0100, since it isnecessary to make bit 2 = 1 to exclude slave 2.The Broadcast Address for each slave is created by taking thelogical OR of SADDR and SADEN. Zeros in this result are trendedas don’t-cares. In most cases, interpreting the don’t-cares as ones,the broadcast address will be FF hexadecimal.Upon reset SADDR (SFR address 0A9H) and SADEN (SFRaddress 0B9H) are leaded with 0s. This produces a given addressof all “don’t cares” as well as a Broadcast address of all “don’tcares”. This effectively disables the Automatic Addressing mode andallows the microcontroller to use standard 80C51 type UART driverswhich do not make use of this feature.Product specification

80C51 8-bit microcontroller family

8XC52/54/58/80C328K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), 8XC51FA/FB/FC/80C51FA

low power, high speed (33MHz)8XC51RA+/RB+/RC+/RD+/80C51RA+

SCON Address = 98HReset Value = 0000 0000B

Bit Addressable

SM0/FE

SM1

SM2RENTB8RB8TlRlBit:

765

4

3

2

1

0

(SMOD0 = 0/1)*

SymbolFunction

FEFraming Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by validframes but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.SM0Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)SM1

Serial Port Mode Bit 1SM0SM1ModeDescriptionBaud Rate**000shift registerfOSC/120118-bit UARTvariable

1029-bit UARTfOSC/64 or fOSC/321

1

3

9-bit UART

variable

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless thereceived 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is aGiven or Broadcast Address. In Mode 0, SM2 should be 0.

RENEnables serial reception. Set by software to enable reception. Clear by software to disable reception.TB8The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

RB8In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used.

TlTransmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in theother modes, in any serial transmission. Must be cleared by software.

Rl

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time inthe other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0 is located at PCON6.**fOSC = oscillator frequency

SU00043Figure 7. SCON: Serial Port Control Register

1999 Apr 01

Product specification80C51 8-bit microcontroller family8XC52/54/58/80C328K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), 8XC51FA/FB/FC/80C51FAlow power, high speed (33MHz)8XC51RA+/RB+/RC+/RD+/80C51RA+D0D1D2D3D4D5D6D7D8START DATA BYTEBITONLY IN MODE 2, 3STOP BITSET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)SM0 TO UART MODE CONTROLSM0 / FESM1SM2RENTB8RB8TIRISCON(98H)SMOD1SMOD0–POFGF1GF0PDIDLPCON(87H)0 : SCON.7 = SM01 : SCON.7 = FESU01191Figure 8. UART Framing Error DetectionD0D1D2D3D4D5D6D7D8SM0SM1SM2RENTB8RB8TIRISCON(98H)1111X10RECEIVED ADDRESS D0 TO D7PROGRAMMED ADDRESSCOMPARATORIN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.SU00045Figure 9. UART Multiprocessor Communication, Automatic Address Recognition1999 Apr 01Product specification80C51 8-bit microcontroller family8XC52/54/58/80C328K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), 8XC51FA/FB/FC/80C51FAlow power, high speed (33MHz)8XC51RA+/RB+/RC+/RD+/80C51RA+Interrupt Priority StructureThe priority scheme for servicing the interrupts is the same as thatThe 8XC51FA/FB/FC and 8XC51RA+/RB+/RC+/RD+ have afor the 80C51, except there are four interrupt levels rather than two7-source four-level interrupt structure (see Table 8). Theas on the 80C51. An interrupt will be serviced as long as an interrupt80C52/54/58 and 80C32 only have a 6-source four-level interruptof equal or higher priority is not already being serviced. If anstructure because these devices do not have a PCA.interrupt of equal or higher level priority is being serviced, the newThere are 3 SFRs associated with the four-level interrupt. They areinterrupt will wait until it is finished before being serviced. If a lowerthe IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interruptpriority level interrupt is being serviced, it will be stopped and thePriority High) register makes the four-level interrupt structurenew interrupt serviced. When the new interrupt is finished, the lowerpossible. The IPH is located at SFR address B7H. The structure ofpriority level interrupt that was stopped will be completed.the IPH register and a description of its bits is shown in Figure 12.The function of the IPH SFR is simple and when combined with theIP SFR determines the priority of each interrupt. The priority of eachinterrupt is determined as shown in the following table:PRIORITY BITSIPH.xIP.xINTERRUPTINTERRUPT PRIORITY LEVELPRIORITYLEVEL00Level 0 (lowest priority)01Level 110Level 211Level 3 (highest priority)Table 8. Interrupt TableSOURCEPOLLING PRIORITYREQUEST BITSHARDWARE CLEAR?VECTOR ADDRESSX01IE0N (L)1Y (T)203HT02TF0Y0BX13IE1N (L)Y (T)13T14TF1Y1BPCA5CF, CCFnN33n = 0–4SP6RI, TIN23T27TF2, EXF2N2BNOTES:1.L = Level activated2.T = Transition activated76543210IE (0A8H)EAECET2ESET1EX1ET0EX0Enable Bit = 1 enables the interrupt.Enable Bit = 0 disables it.BITSYMBOLFUNCTIONIE.7EAGlobal disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individuallyenabled or disabled by setting or clearing its enable bit.IE.6ECPCA interrupt enable bit for FX and RX+ only – otherwise it is not implemented.IE.5ET2Timer 2 interrupt enable bit.IE.4ESSerial Port interrupt enable bit.IE.3ET1Timer 1 interrupt enable bit.IE.2EX1External interrupt 1 enable bit.IE.1ET0Timer 0 interrupt enable bit.IE.0EX0External interrupt 0 enable bit.SU00840Figure 10. IE Registers1999 Apr 01Product specification

80C51 8-bit microcontroller family

8XC52/54/58/80C328K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), 8XC51FA/FB/FC/80C51FA

low power, high speed (33MHz)8XC51RA+/RB+/RC+/RD+/80C51RA+

7

6543210IP (0B8H)

—

PPC

PT2

PS

PT1

PX1

PT0

PX0

Priority Bit = 1 assigns high priorityPriority Bit = 0 assigns low priority

BITSYMBOLFUNCTION

IP.7—Not implemented, reserved for future use.

IP.6PPCPCA interrupt priority bit for FX and RX+ only, otherwise it is not implemented.IP.5PT2Timer 2 interrupt priority bit.IP.4PSSerial Port interrupt priority bit.IP.3PT1Timer 1 interrupt priority bit.IP.2PX1External interrupt 1 priority bit.IP.1PT0Timer 0 interrupt priority bit.IP.0

PX0

External interrupt 0 priority bit.SU00841Figure 11. IP Registers

1999 Apr 01