ST16C1550IP28资料

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OCTOBER 2003 FEATURES2.97V TO 5.5V UART WITH 16-BYTE FIFO

ST16C1550/51

REV. 4.2.0GENERAL DESCRIPTION

The ST16C1550 and ST16C1551 UARTs (here ondenoted as the ST16C155X) are improved versionsof the SSI 73M1550 and SSI 73M2550 UART withhigher operating speed and lower access time. TheST16C155X provides enhanced UART functions with16 byte FIFOs, a modem control interface,independent programmable baud rate generatorswith clock rates up to 1.5 Mbps. Onboard statusregisters provide the user with error indications andoperational status. System interrupt and modemcontrol features may be tailored by external softwareto meet specific user requirements. An internalloopback capability allows onboard diagnostics. Thebaud rate generator can be configured for eithercrystal or external clock input with the exception ofthe 28 pin ST16C1551 package (where an externalclock must be provided). Each package type, with theexception of the 28 pin ST16C155X, provides abuffered reset output that can be controlled throughuser software. DMA monitor signals TXRDY/RXRDYare not available at the ST16C155X I/O pins butthese signals are accessible through ISR register bits4-5. Except as listed above, all package versionshave the same features. The ST16C155X is notcompatible with the industry standard 16550 and willnot work with the standard serial port driver in MSWindows (see pages 16-17 for details). For an MSWindows compatible UART, see the ST16C550.

•Pin and functionally compatible to SSI 73M1550/

2550

•16 byte Transmit FIFO

•16 byte Receive FIFO with error flags

•4 selectable Receive FIFO interrupt trigger levels•Modem Control Signals (CTS#, RTS#, DSR#,

DTR#, RI#, CD#)

•Programmable character lengths (5, 6, 7, 8) with

even, odd or no parity

•Crystal or external clock input (except 28 pin

ST16C1551, external clock only)

•1.5 Mbps Transmit/Receive operation (24 MHz)

with programmable clock control

•Power Down Mode (50 uA at 3.3 V, 200 uA at 5 V)•Software controllable reset output•2.97 to 5.5 Volt operation

APPLICATIONS•Battery Operated Electronics•Internet Appliances•Handheld Terminal

•Personal Digital Assistants•Cellular Phones DataPort

FIGURE 1. BLOCK DIAGRAM

16 Byte TX FIFOA2:A0D7:D0IOR#IOW#CS#Data BusInterfaceUARTConfigurationRegsDTR#, RTS#Modem Control SignalsDSR#, CTS#,CD#, RI#TransmitterTXINTReceiver16 Byte RX FIFORXBaud Rate GeneratorRESETRSTXTAL1/CLKXTAL2Crystal Osc/BufferExar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFOFIGURE 2. ST16C1550 PINOUTS

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REV. 4.2.048-TQFP PACKAGEDSR#VCCN.C.N.C.N.C.CD#N.C.N.C.D3D2D1D0NOTE: PINOUTS NOT TO SCALE.ACTUAL SIZE OF TQFP PACKAGEIS SMALLER THAN PLCC PACKAGE.484744434241403938N.C.N.C.D4D5D6D7RXTXCS#N.C.N.C.N.C.1234567101112131415161718192021222324373635343332N.C.N.C.CTS#RESETDTR#RTS#A0N.C.A1A2N.C.N.C.ST16C1550CQ483130292827262528-PDIP PACKAGESD0D1D2D3D4123428272625VCCCD#DSR#CTS#RESETDTR#RTS#A0A1A2INTRI#IOR#GNDXTAL1XTAL2RSTN.C.N.C.N.C.GNDIOW#IOR#N.C.RI#INT5671011121314ST16C1550CP282423222120191817161528-PLCC PACKAGES26DSR#VCCD3D2D1D0CD#D5D6D7RX28274321D4D5D6D7RXTX56710252423CTS#RESETDTR#RTS#A0A1A2TXCS#XTAL1XTAL2IOW#ST16C1550CJ2822212019CS#11121314151617RI#18INTXTAL1XTAL2GNDIOW#IOR#2

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REV. 4.2.0áç

FIGURE 3. ST16C1551 PINOUTS

48-TQFP PACKAGEDSR#VCCN.C.N.C.N.C.CD#N.C.N.C.D3D2D1D0 ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

NOTE: PINOUTS NOT TO SCALE.ACTUAL SIZE OF TQFP PACKAGEIS SMALLER THAN PLCC PACKAGE.484744434241403938N.C.N.C.D4D5D6D7RXTXCS#N.C.N.C.N.C.1234567101112131415161718192021222324373635343332N.C.N.C.CTS#RESETDTR#RTS#A0N.C.A1A2N.C.N.C.ST16C1551CQ483130292827262528-PDIP PACKAGESD0D1123428272625VCCCD#DSR#CTS#RESETDTR#RTS#A0A1A2INTRSTRI#IOR#XTAL1XTAL2RSTN.C.N.C.N.C.GNDIOW#IOR#N.C.RI#INTD2D3D45671011121314ST16C1551CP282423222120191817161528-PLCC PACKAGES26DSR#VCCCD#D3D2D1D0D5D6D7RXTX28D4D5D6D7RXTX27432156710252423CTS#RESETDTR#RTS#A0A1A2CS#CLKIOW#GNDST16C1551CJ2822212019CS#1112IOW#1314151617RST18INTCLKGNDIOR#RI#3

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

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REV. 4.2.0ORDERING INFORMATIONOPERATING

PART NUMBERST16C1550CP28ST16C1550CJ28ST16C1550CQ48ST16C1551CP28ST16C1551CJ28ST16C1551CQ48ST16C1550IP28ST16C1550IJ28ST16C1550IQ48ST16C1551IP28ST16C1551IJ28ST16C1551IQ48

PACKAGE28-Lead PDIP28-Lead PLCC48-Lead TQFP28-Lead PDIP28-Lead PLCC48-Lead TQFP28-Lead PDIP28-Lead PLCC48-Lead TQFP28-Lead PDIP28-Lead PLCC48-Lead TQFP

TEMPERATURE

RANGE0°C to +70°C0°C to +70°C0°C to +70°C0°C to +70°C0°C to +70°C0°C to +70°C

DEVICE STATUS

Discontinued. See the ST16C1550CQ48 for a replacement.ActiveActive

Discontinued. See the ST16C1551CQ48 for a replacement.ActiveActive

-40°C to +85°CDiscontinued. See the ST16C1550IQ48 for a replacement.-40°C to +85°CActive-40°C to +85°CActive

-40°C to +85°CDiscontinued. See the ST16C1551IQ48 for a replacement.-40°C to +85°CActive-40°C to +85°CActive

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REV. 4.2.0áç

28-PIN 28-PIN28-PIN 28-PIN

48-PIN

TYPEPDIP PDIP PLCCPLCC

TQFP

(1550)(1551)(1550)(1551)

ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

PIN DESCRIPTIONS

NAME

DESCRIPTION

DATA BUS INTERFACEA0A1A2D0D1D2D3D4D5D6D7IOR#

2120191234567816

2120191234567815

2120191234567816

2120191234567815

3028274347345620

Address data lines [2:0]. A2:A0 selects internal UART’s configuration registers.

I/OData bus lines [7:0] (bidirectional).

Input/Output Read (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], places it on the data bus to allow the host processor to read it on the leading edge.

Input/Output Write (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines [A2:A0].

Chip Select input (active low). A logic 0 on this pin selects the ST16C155X device.

Interrupt Output (three-state, active high). INT output

defaults to three-state mode and becomes active high when MCR bit-3 is set to a logic 1. INT output becomes a logic high level when interrupts are enabled in the interrupt enable register (IER), and whenever the transmitter,

receiver, line and/or modem status register has an active condition.

IOW#1413141317I

CS#INT

1118

923

MODEM OR SERIAL I/O INTERFACETX

Transmit Data. This output is associated with individual serial transmit channel data from the 155X. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the TX output pin is disabled and TX data is internally con-nected to the UART RX input.

Receive Data. This input is associated with individual serial channel data to the 155X. Normal received data input idles at logic 1 condition. This input must be connected to its idle logic state, logic 1, else the receiver may report “receive break” and/or “error” condition(s).

RX99997I

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

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REV. 4.2.0NAMERTS#

28-PIN 28-PIN28-PIN 28-PIN

48-PIN

PDIP PDIP PLCCPLCCTQFPTYPE (1550)(1551)(1550)(1551)22

DESCRIPTION

Request to Send or general purpose output (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, leave it uncon-nected.

Clear to Send or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC.Data Terminal Ready or general purpose output (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, leave it unconnected.

Data Set Ready input or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC.

Carrier Detect input or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC.Ring Indicator input or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC.

CTS#2525252534I

DTR#2323232332O

DSR#2626262639I

CD#2727272740I

RI#1716171621I

ANCILLARY SIGNALSCLK

-12

-I

External Clock Input. This function is associated with 28 pin PDIP and 28 pin PLCC packages only. An external clock must be connected to this pin to clock the baud rate genera-tor and internal circuitry.

Crystal or external clock input. See Figure4 for typical oscillator connections.

Crystal or buffered clock output. See Figure4 for typical oscillator connections.

Reset Input (active high). When it is asserted, the UART configuration registers are reset to default values, see Table8.

Reset Output (active high). This output is only available on the ST16C1551. When IER bit-5 is a logic 0, RST will follow the logical state of the RESET pin. When IER bit-5 is a logic 1, the user may send software (soft) resets via MCR bit-2. Soft resets from MCR bit-2 are “ORed” with the state of the RESET pin.

XTAL1XTAL2RESET

121324

--24

121324

--24

151633

IOI

RST-17-1722O

VCC2828282841PwrPowersupplyinput.

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REV. 4.2.0áç

NAMEGNDN.C.

28-PIN 28-PIN28-PIN 28-PIN

48-PIN

PDIP PDIP PLCCPLCCTQFPTYPE(1550)(1551)(1550)(1551)15-14-15-14-191,2,10-14,18,24-26,29,35-38,42, 44, 48

ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

DESCRIPTION

PwrPower supply common ground. -Not connected.

Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.

1.0PRODUCT DESCRIPTION

The ST16C155X provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary forconverting the serial data stream into parallel data that is required in digital data systems. Synchronization forthe serial data stream is accomplished by adding start and stops bits to the transmit data to form a datacharacter (character orientated protocol). Data integrity is ensured by attaching a parity bit to the datacharacter. The parity bit is checked by the receiver for any transmission bit errors. ENHANCED FEATURES

The ST16C155X is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of

none in the 16C145X. The 155X is designed to work with high speed modems and shared network

environments, that require fast data processing time. Increased performance is realized in the 155X by the

larger transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a

given time. For example, the ST16C550 with a 16 byte FIFO, unloads 16 bytes of receive data in 93microseconds (This example uses a character length of 11 bits, including start/stop bits at 115.2Kbps). Thismeans the external CPU will have to service the receive FIFO less than every 100 microseconds. Howeverwith the 16 byte FIFO in the 155X, the data buffer will not require unloading/loading for 1.53 ms. This increasesthe service interval giving the external CPU additional time for other applications and reducing the overallUART interrupt servicing time. In addition, the 4 selectable levels of FIFO trigger interrupt are provided formaximum data throughput performance especially when operating in a multi-channel environment. The FIFOmemory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance,and reduces power consumption.

DATA RATE

The 155X is capable of operation up to 1.5 Mbps with a 24 MHz crystal or external clock input with a 16Xsampling clock (at VCC = 5.0V). With a crystal of 14.7456 MHz and through a software option, the user canselect data rates up to 921.6 Kbps.

The rich feature set of the 155X is available through internal registers. Selectable receive FIFO trigger levels,selectable baud rates, and modem interface controls are all standard features. Following a power on reset oran external reset, the 155X is software compatible with the ST16C145X.

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO2.0FUNCTIONAL DESCRIPTIONS2.1

Internal Registers

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REV. 4.2.0The 155X has a set of enhanced registers for controlling, monitoring and data loading and unloading. Theseregisters function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFOcontrol register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers(MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scractchpadregister (SPR). All the register functions are discussed in full detail later in “Section 3.0, UART INTERNALREGISTERS” on page14.2.2

DMA Mode

The DMA Mode (a legacy term) in this document does not mean “Direct Memory Access” but refers to datablock transfer operation. The DMA mode affects the state of the RXRDY and TXRDY bits (ISR bits 5 and 4respectively). The transmit and receive FIFO trigger levels provide additional flexibility to the user for blockmode operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an emptylocation(s) for more data. The user can optionally operate the transmit and receive FIFO in the DMA mode(FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 =0), the 155X activates the TXRDY & RXRDY output pin for each data transmit or receive operation. WhenDMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading orunloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the 155Xsets the TXRDY bit when the transmit FIFO becomes full, and sets the RXRDY pin when the receive FIFObecomes empty. The following table shows their behavior.

TABLE 1: TXRDY AND RXRDY BITS IN FIFO AND DMA MODE

PINS

FCR BIT-0=0(FIFO DISABLED)

FCR BIT-0=1 (FIFO ENABLED)

FCR Bit-3 = 0

(DMA Mode Disabled)

RXRDY

1 = 1 byte0 = no data1 = THR empty0 = byte in THR

1 = at least 1 byte in FIFO 0 = FIFO empty

1 = FIFO empty

0 = at least 1 byte in FIFO

FCR Bit-3 = 1(DMA Mode Enabled)

1 = FIFO reaches the trigger level, or timeout occurs

0 = FIFO empty

1 = FIFO has at least 1 empty location0 = FIFO is full

TXRDY

2.3Crystal Oscillator or External Clock

The 155X includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clockto the Baud Rate Generators (BRG) in the UART. XTAL1 is the input to the oscillator or external clock bufferinput with XTAL2 pin being the output. For programming details, see “Section 2.4, Programmable Baud RateGenerator” on page9.

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequencytolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure4). Alternatively, an externalclock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates.Typical oscillator connections are shown in Figure4. For further reading on oscillator circuit please seeapplication note DAN108 on EXAR’s web site.

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REV. 4.2.0áç

ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS

XTAL1XTAL2R10-120(Optional)R2500K - 1MY11.8432 MHzto24 MHzC122-47pFC222-47pF2.4Programmable Baud Rate Generator

The UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a softwarebit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external clock by1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by aprogrammable divisor between 1 and (216 -1) to obtain a 16X sampling clock of the serial data rate. Thesampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor(DLL and DLM registers) defaults to a random value upon power up or a reset. Therefore, the BRG must beprogrammed during initialization to the operating data rate. Programming the Baud Rate Generator RegistersDLM and DLL provides the capability of selecting the operating data rate. Table2 shows the standard datarates available with a 14.7456 MHz crystal or external clock at 16X clock rate. When using a non-standard datarate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.

divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

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REV. 4.2.0TABLE 2: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK

OUTPUT Data Rate OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x MCR Bit-7=1MCR Bit-7=0Clock (Decimal)Clock (HEX)

100600120024004800960019.2k 38.4k57.6k

40024004800960019.2k38.4k76.8k153.6k230.4k

230438419298241221

900180C06030180C06040201

DLM PROGRAM

VALUE (HEX)

0901000000000000000000

DLL PROGRAM VALUE (HEX)

00 80 C0 60 30 18 0C 06 04

DATA RATE ERROR (%)

000000000

115.2k 460.8k230.4k

921.6k

020 01

2.5Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which

includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internalclock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported inthe Line Status Register (LSR bit-5 and bit-6). 2.5.1

Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The hostwrites transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the inputregister to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a writeoperation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential datalocation. 2.5.2

Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when thedata byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabledby IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

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REV. 4.2.0áç

ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

FIGURE 5. TRANSMITTER OPERATION IN NON-FIFO MODE

DataByteTransmitHoldingRegister(THR)THR Interrupt (ISR bit-1)Enabled by IER bit-116X ClockTransmit Shift Register (TSR)MSBLSBTXNOFIFO12.5.3Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is setwhenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when theamount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled byIER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.2.6

Receiver

The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes abyte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validatesevery bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be atthe center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluatingthe start bit in this manner prevents the receiver from assembling a false character. The rest of the data bitsand stop bits are sampled and validated in this same manner to prevent false framing. If there were anyerror(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, thereceive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the databyte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay untilit reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data readytime-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This isequivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.2.6.1

Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive ShiftRegister. It provides the receive data interface to the host processor. The RHR register is part of the receiveFIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. Whenthe FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After theRHR is read, the next character byte is loaded into the RHR and the errors associated with the current databyte are immediately updated in the LSR bits 2-4.

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

FIGURE 6. RECEIVER OPERATION IN NON-FIFO MODE

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REV. 4.2.016X ClockReceive Data ShiftRegister (RSR)Data BitValidationReceive Data CharactersReceiveData Byteand ErrorsErrorTags inLSR bits4:2Receive DataHolding Register(RHR)RHR Interrupt (ISR bit-2)RXFIFO12.7Special (Enhanced Feature) Mode

The 155X supports the standard features of the ST16C550. In addition the 155X supports some enhancedfeatures not available for the ST16C550. These features are enabled by IER bit-5 and include a softwarecontrollable (SOFT) reset, power down feature and FIFO monitoring bits. 2.7.1

Soft Reset

Soft resets are useful when the user desires the capability of resetting an externally connected device only.MCR bit-2 can be used to initiate a SOFT reset at the RST output pin. This does not reset the 155X (only theRESET input pin can reset the 155X). Soft resets from MCR bit-2 are “ORed” with the RESET input pin.Therefore both reset types will be seen at the RST output pin.2.7.2

Power Down Mode

The power down feature (controlled by MCR bit-7) provides the user with the capability to conserve powerwhen the package is not in actual use without destroying internal register configuration data. This allows quickturnarounds from power down to normal operation. 2.7.3

TXRDY and RXRDY bits

When IER bit-5 is set to a logic 1, ISR bits 4 and 5 represent the compliment (inversion) of the TXRDY statusand RXRDY status, respectively. See Table1.2.8

Internal Loopback

The 155X UART provides an internal loopback capability for system diagnostic purposes. The internalloopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.Figure7 shows how the modem port signals are re-configured. Transmit data from the transmit shift registeroutput is internally routed to the receive shift register input allowing the system to receive the same data that itwas sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, andCTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopbacktest else upon exiting the loopback test the UART may detect and report a false “break” signal.

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REV. 4.2.0áç

FIGURE 7. INTERNAL LOOPBACK

ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

VCCTransmit Shift Register(THR/FIFO)MCR bit-4=1Internal Data Bus Lines and Control SignalsReceive Shift Register(RHR/FIFO)VCCRTS#Modem / General Purpose Control LogicRTS#TXRXCTS#VCCDTR#DSR#CTS#DTR#DSR#OP1#RI#RI#OP2#CD#CD#13

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO3.0UART INTERNAL REGISTERS

The 155X has a set of configuration registers selected by address lines A0, A1 and A2. The 16C550compatible registers can be accessed when LCR[7] = 0 and the baud rate generator divisor registers can beaccessed when LCR[7] = 1. The complete register set is shown on Table3 and Table4.

TABLE 3: ST16C155X UART INTERNAL REGISTERS

A2,A1,A0 ADDRESSES 0 0 00 0 00 0 10 0 10 1 00 1 11 0 01 0 11 1 01 1 1

REGISTERRHR - Receive Holding Register THR - Transmit Holding RegisterDLL - Div Latch Low ByteDLM - Div Latch High ByteIER - Interrupt Enable RegisterISR - Interrupt Status RegisterFCR - FIFO Control RegisterLCR - Line Control RegisterMCR - Modem Control RegisterLSR - Line Status RegisterReserved

MSR - Modem Status RegisterReserved

SPR - Scratch Pad Register

READ/WRITERead-onlyWrite-onlyRead/WriteRead/WriteRead/WriteRead-onlyWrite-onlyRead/WriteRead/WriteRead-onlyWrite-onlyRead-onlyWrite-onlyRead/Write

LCR[7] = 0COMMENTSLCR[7] = 0

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REV. 4.2.0LCR[7] = 1

LCR[7] = 0

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REV. 4.2.0áç

ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

TABLE 4: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

ADDRESSA2-A0

REGNAME

READ/WRITE

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

16C550 Compatible Registers

0 0 0 0 0 0 0 0 1

RHRTHRIER

RDWRRD/WR

Bit-7Bit-70

Bit-6Bit-60

Bit-5Bit-5Special Mode Enable

(Enable ISR bits 5-4, FCR bits 5-4, MCR bits 7, 2)

Bit-4Bit-40

Bit-3Bit-3

Bit-2Bit-2

Bit-1Bit-1

Bit-0Bit-0

Modem RX Line TX RX Status Status Empty Data

Int. Int. Int. Int.

EnableEnableEnableEnable

LCR[7] = 0

0/TXRDY

INT Source Bit-3DMA Mode Enable

INT INT INT Source Source Source Bit-2Bit-1Bit-0TX FIFO Reset

RX FIFO Reset

FIFOs Enable

0 1 0ISRRD

FIFOs FIFOs EnabledEnabled

0/RXRDY

0 1 0FCRWR

RX FIFO RX FIFO 0/0/TriggerTrigger

TX FIFO TX FIFO

(MSB)(LSB)

TriggerTrigger(MSB)(LSB)Divisor

Enable0/Power Down Mode

Set TX Break0

Set Parity0

Even ParityInternal Loop-back EnableRX Break

0 1 1LCRRD/WR

Parity EnableStop Bits

Word Word LengthLength

Bit-0Bit-1

1 0 0MCRRD/WR

(OP2#)/(OP1#)/RTS# DTR#

INT Output Output

SOFT ControlControl

Output

Reset

EnableRXFraming ErrorDelta CD#Bit-3

RX RX Parity Over-Errorrun

ErrorDelta RI#Bit-2

Delta DSR#Bit-1

RX Data ReadyDelta CTS#Bit-0

1 0 1LSRRD

RX FIFO THR & Global TSR ErrorEmptyCD# InputBit-7

RI# InputBit-6

THR Empty

LCR[7] = 0

1 1 0 1 1 1

MSRSPR

RDRD/WR

DSR# Input Bit-5

CTS# InputBit-4

Baud Rate Generator Divisor

0 0 0 0 0 1

DLLDLM

RD/WRRD/WR

Bit-7Bit-7

Bit-6Bit-6

Bit-5Bit-5

Bit-4Bit-4

Bit-3Bit-3

Bit-2Bit-2

Bit-1Bit-1

Bit-0Bit-0

LCR[7] = 1

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO4.0INTERNAL REGISTER DESCRIPTIONS4.14.24.3

Receive Holding Register (RHR) - Read- OnlyTransmit Holding Register (THR) - Write-OnlyInterrupt Enable Register (IER) - Read/Write

See “Receiver” on page11.See “Transmitter” on page10.

The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line statusand modem status registers. These interrupts are reported in the Interrupt Status Register (ISR). 4.3.1

IER versus Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts(see ISR bits 2 and 3) status will reflect the following:

A.The receive data available interrupts are issued to the host when the FIFO has reached the programmed

trigger level. It will be cleared when the FIFO drops below the programmed trigger level.B.FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register

status bit and the interrupt will be cleared when the FIFO drops below the trigger level.C.The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to

the receive FIFO. It is reset when the FIFO is empty.4.3.2

IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C155X in the FIFOpolled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both canbe used in the polled mode by selecting respective transmit or receive control bit(s).A.LSR BIT-0 indicates there is data in RHR or RX FIFO.

B.LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.C.LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.D.LSR BIT-5 indicates THR is empty.

E.LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.F.LSR BIT-7 indicates a data error in at least one character in the RX FIFO.IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or whenthe receive FIFO has reached the programmed trigger level in the FIFO mode.

áç

REV. 4.2.0•Logic 0 = Disable the receive data ready interrupt (default).•Logic 1 = Enable the receiver data ready interrupt.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the THR is empty in the non-FIFOmode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is emptywhen this bit is enabled, an interrupt will be generated. Note that this interrupt does not behave in the samemanner as the industry standard 16C550. See “Interrupt Clearing:” on page17.

•Logic 0 = Disable Transmit Ready interrupt (default).•Logic 1 = Enable Transmit Ready interrupt.

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controllerabout the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when thecharacter has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out ofthe FIFO.

•Logic 0 = Disable the receiver line status interrupt (default).•Logic 1 = Enable the receiver line status interrupt.

IER[3]: Modem Status Interrupt Enable

•Logic 0 = Disable the modem status register interrupt (default).•Logic 1 = Enable the modem status register interrupt.

IER[4]: Reserved

IER[5]: Special Mode Enable

•Logic 0 = Disable special mode functions (default).

•Logic 1 = Enable special mode functions in addition to basic ST16C1450 functions. Enables ISR bits 4-5

(TXRDY/RXRDY), MCR bit-2 (soft reset) and MCR bit-7 (power down) functions.IER[7:6]: Reserved4.4

Interrupt Status Register (ISR) - Read-Only

The UART provides multiple levels of prioritized interrupts to minimize external software interaction. TheInterrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on theISR will give the user the current highest pending interrupt level to be serviced, others are queued up to beserviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The InterruptSource Table, Table5, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sourcesassociated with each of these interrupt levels.4.4.1

Interrupt Generation:

•LSR is by any of the LSR bits 1, 2, 3 and 4.•RXRDY is by RX trigger level.

•RXRDY Time-out is by a 4-char plus 12 bits delay timer.•TXRDY is by TX trigger level or TX FIFO empty.•MSR is by any of the MSR bits 0, 1, 2 and 3.

4.4.2

Interrupt Clearing:

•LSR interrupt is cleared by a read to the LSR register (but flags and tags not cleared until character(s) that

generated the interrupt(s) has been emptied or cleared from FIFO).

•RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.•RXRDY Time-out interrupt is cleared by reading RHR until empty.

•TXRDY interrupt is cleared by a read to the ISR register AND disabling the TXRDY interrupt (set IER bit-1 =0), or by loading data into the TX FIFO.•MSR interrupt is cleared by a read to the MSR register.

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

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REV. 4.2.0TABLE 5: INTERRUPT SOURCE AND PRIORITY LEVEL

PRIORITY LEVEL

ISR REGISTER STATUS BITSBIT-3

12345-010000

BIT-2111000

BIT-1100100

BIT-0000001

LSR (Receiver Line Status Register)RXRDY (Receive Data Time-out)RXRDY (Received Data Ready)TXRDY (Transmit Ready)MSR (Modem Status Register)None (default)

SOURCE OF INTERRUPT

ISR[0]: Interrupt Status

•Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

service routine.

•Logic 1 = No interrupt pending (default condition).

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table5). ISR[4]: TXRDY

This bit represents the compliment (inversion) of the TXRDY status when IER bit-5 is set to a logic 1. SeeTable1.ISR[5]: RXRDY

This bit represents the compliment (inversion) of the RXRDY status when IER bit-5 is set to a logic 1. SeeTable1.

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs areenabled. 4.5

FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, andselect the DMA mode. The DMA, and FIFO modes are defined as follows:FCR[0]: TX and RX FIFO Enable

•Logic 0 = Disable the transmit and receive FIFO (default).

•Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are

written or they will not be programmed.FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

•Logic 0 = No receive FIFO reset (default).

•Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

•Logic 0 = No transmit FIFO reset (default).

•Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.FCR[3]: DMA Mode Select

Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.

•Logic 0 = Normal Operation (default).•Logic 1 = DMA Mode.

FCR[5:4]: Transmit FIFO Trigger Select

These 2 bits are only active when IER bit-5 is a ‘1’.(logic 0 = default, TX trigger level = 1)

These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when thenumber of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that theFIFO did not get filled over the trigger level on last re-load. Table6 shows the selections. FCR[7:6]: Receive FIFO Trigger Select(logic 0 = default, RX trigger level =1)

These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt whenthe number of the characters in the FIFO crosses the trigger level. Table6 shows the complete selections.

TABLE 6: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION

FCR BIT-7

FCR BIT-6

FCR BIT-50011

0011

0101

FCR BIT-40101

14814

RECEIVE TRANSMIT TRIGGER TRIGGER LEVELLEVEL

4814

4.6Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word orcharacter length, the number of stop bits, and the parity are selected by writing the appropriate bits in thisregister.

LCR[1:0]: TX and RX Word Length Select

These two bits specify the word length to be transmitted or received.

BIT-100

BIT-001

WORD LENGTH5 (default)

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

BIT-111

BIT-001

WORD LENGTH7

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REV. 4.2.0LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in conjunction with the programmed word length.

BIT-2011

WORD

LENGTH

STOP BIT LENGTH(BIT TIME(S))1 (default)1-1/22

5,6,7,856,7,8

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for dataintegrity check. See Table7 for parity selection summary below.

•Logic 0 = No parity.

•Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the

data character received.LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.

•Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format (default).

•Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format.LCR[5]: TX and RX Parity Select

If the parity bit is enabled, LCR BIT-5 selects the forced parity format.

•LCR[5] = logic 0, parity is not forced (default).

•LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.•LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.

TABLE 7: PARITY SELECTION

LCR BIT-5LCR BIT-4LCR BIT-3

X0011

X0101

01111

PARITY SELECTION

No parityOdd parityEvenparityForce parity to mark,

“1”Forced parity to space, “0”

LCR[6]: Transmit Break Enable

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.

•Logic 0 = No TX break condition (default).

•Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line

break condition.

LCR[7]: Baud Rate Divisors Enable

Baud rate generator divisor (DLL/DLM) enable.

•Logic 0 = Data registers are selected (default).•Logic 1 = Divisor latch registers are selected.

4.7

Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write

The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as ageneral purpose output.

•Logic 0 = Force DTR# output to a logic 1 (default).•Logic 1 = Force DTR# output to a logic 0.

MCR[1]: RTS# Output

The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as ageneral purpose output.

•Logic 0 = Force RTS# output to a logic 1 (default).•Logic 1 = Force RTS# output to a logic 0.

MCR[2]: OP1# Output/Soft Reset

OP1# is not available as an output pin on the 155X. But it is available for use during Internal Loopback Mode.In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.

•Logic 0 = OP1# output (RI# input) is at logic 1 (default). •Logic 1 = OP1# output (RI# input) is at logic 0.

In normal operation, this bit is associated with the RST (buffered reset) output pin. The logical state of the RSTpin will follow exactly the logical state of the RESET pin. When IER bit-5 = 1, soft resets from MCR bit-2 areORed with the state of the RESET input pin. Therefore both reset types will be seen at the RST pin. Note thatasserting MCR bit-2 does not reset the 155X.

•Logic 0 = The RST output pin is a logic 0 (default). •Logic 1 = The RST output pin is a logic 1.

MCR[3]: OP2# or INT Output EnableWhen not in Internal Loopback Mode:

•Logic 0 = INT output is three-state (default).•Logic 1 = INT output is active high.

OP2# is not available as an output pin on the 155X. But it is available for use during Internal Loopback Mode.In the Loopback Mode, this bit is used to write the state of the modem CD# interface signal.

•Logic 0 = OP2# output (CD# input) is a logic 1 (default). •Logic 1 = OP2# output (CD# input) is a logic 0.

MCR[4]: Internal Loopback Enable

•Logic 0 = Disable loopback mode (default).

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

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REV. 4.2.0•Logic 1 = Enable local loopback mode, see loopback section and Figure7.

MCR[6:5]: Reserved MCR[7]: Power Down Enable

This bit can only be accessed when IER bit-5 = 1.

•Logic 0 = Normal mode (default).

•Logic 1 = Power down mode. See “Power Down Mode” on page12.

4.8

Line Status Register (LSR) - Read Only

This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic1, an LSR interrupt will be generated when the character that is ready to be read from the RX FIFO has anerror (parity, framing, overrun, break).LSR[0]: Receive Data Ready Indicator

•Logic 0 = No data in receive holding register or FIFO (default).

•Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

LSR[1]: Receiver Overrun Error Flag

•Logic 0 = No overrun error (default).

•Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens

when additional data arrives while the FIFO is full. In this case the previous data in the receive shift registeris overwritten. Note that under this condition the data byte in the receive shift register is not transferred intothe FIFO, therefore the data in the FIFO is not corrupted by the error. LSR[2]: Receive Data Parity Error Tag

•Logic 0 = No parity error (default).

•Logic 1 = Parity error. The received character in RHR does not have correct parity information and is

suspect. This error is associated with the character available for reading in RHR. LSR[3]: Receive Data Framing Error Tag

•Logic 0 = No framing error (default).

•Logic 1 = Framing error. The received character did not have a valid stop bit(s). This error is associated with

the character available for reading in RHR.LSR[4]: Receive Break Error Tag

•Logic 0 = No break condition (default).

•Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the

FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RXinput returns to the idle condition, “mark” or logic 1. LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byteis transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is setwhen the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR orTSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO andtransmit shift register are both empty.LSR[7]: Receive FIFO Data Error Flag

•Logic 0 = No FIFO error (default).

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2.97V TO 5.5V UART WITH 16-BYTE FIFO

•Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error

or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in theRX FIFO. 4.9

Modem Status Register (MSR) - Read Only

This register provides the current state of the modem interface input signals. Lower four bits of this register areused to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modemchanges state. These bits may be used for general purpose inputs when they are not used with modemsignals.

MSR[0]: Delta CTS# Input Flag

•Logic 0 = No change on CTS# input (default).

•Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).MSR[1]: Delta DSR# Input Flag

•Logic 0 = No change on DSR# input (default).

•Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).MSR[2]: Delta RI# Input Flag

•Logic 0 = No change on RI# input (default).

•Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status

interrupt will be generated if MSR interrupt is enabled (IER bit-3).MSR[3]: Delta CD# Input Flag

•Logic 0 = No change on CD# input (default).

•Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem

status interrupt will be generated if MSR interrupt is enabled (IER bit-3).MSR[4]: CTS Input Status

CTS# (active high, logical 1). Normally this bit is the compliment of the CTS# input. In the loopback mode, thisbit is equivalent to bit-1 in the MCR register. The CTS# input may be used as a general purpose input when themodem interface is not used.MSR[5]: DSR Input Status

DSR# (active high, logical 1). Normally this bit is the compliment of the DSR# input. In the loopback mode, thisbit is equivalent to bit-0 in the MCR register. The DSR# input may be used as a general purpose input when themodem interface is not used.MSR[6]: RI Input Status

RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit isequivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when themodem interface is not used.MSR[7]: CD Input Status

CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bitis equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when themodem interface is not used.4.10

Scratch Pad Register (SPR) - Read/Write

This is a 8-bit general purpose register for the user to store temporary data. The content of this register ispreserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

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REV. 4.2.0TABLE 8: UART RESET CONDITIONS

REGISTERS

DLLDLMRHRTHRIERFCRISRLCRMCRLSRMSRSPR

Bits 7-0 = 0xXXBits 7-0 = 0xXXBits 7-0 = 0xXXBits 7-0 = 0xXXBits 7-0 = 0x00Bits 7-0 = 0x00Bits 7-0 = 0x01Bits 7-0 = 0x00Bits 7-0 = 0x00Bits 7-0 = 0x60

Bits 3-0 = Logic 0

Bits 7-4 = Logic levels of the inputs invertedBits 7-0 = 0xFF

RESET STATE

I/O SIGNALS

TXRTS#DTR#RSTINT

Logic 1Logic 1Logic 1Logic 1

RESET STATE

Three-State Condition

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REV. 4.2.0áç

ABSOLUTE MAXIMUM RATINGS

Power Supply RangeVoltage at Any PinOperating TemperatureStorage TemperaturePackage Dissipation

ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

7 VoltsGND-0.3 V to 7 V-40o to +85oC-65o to +150oC500 mW

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)Thermal Resistance (48-TQFP)Thermal Resistance (28-PDIP)Thermal Resistance (28-PLCC)

theta-ja = 59oC/W, theta-jc = 16oC/W theta-ja = 57oC/W, theta-jc = 23oC/W theta-ja = 55oC/W, theta-jc = 28oC/W

ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICSUNLESS OTHERWISE NOTED: TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V

SYMBOLVILCKVIHCKVILVIHVOLVOLVOHVOHIILIIHCINICCIPWRDN

PARAMETER

Clock Input Low LevelClock Input High LevelInput Low VoltageInput High VoltageOutput Low VoltageOutput Low VoltageOutput High VoltageOutput High VoltageInput Low Leakage CurrentInput High Leakage CurrentInput Pin CapacitancePower Supply CurrentPower Down Current

2.0

±10±1051.350

±10±1053200

0.4

2.4

LIMITS3.3V

MIN MAX-0.32.4-0.32.0

0.6VCC0.8VCC

LIMITS5.0V

MIN MAX-0.53.0-0.52.2

0.6VCC0.8VCC0.4

UNITSVVVVVVVVuAuApFmAuA

See Test 1IOL = 6 mAIOL = 4 mAIOH = -6 mAIOH = -1 mACONDITIONS

Test 1: The following inputs should remain steady at VCC or GND state to minimize Power Down current: A0-A2, D0-D7,IOR#, IOW#, CS# and modem inputs. Also, RX input must idle at logic 1 state while in Power Down mode.

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

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REV. 4.2.0AC ELECTRICAL CHARACTERISTICS TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5VSYMBOLCLKOSCTASTAHTCSTRDTDYTRDVTDDTWRTDSTDHTWDOTMODTRSITSSITRRITSITINTTSSRTRRTWTTSRTTRSTNBclk

PARAMETER

Clock Pulse Duration

Oscillator/External Clock FrequencyAddress Setup Time Address Hold Time Chip Select WidthIOR# Strobe WidthRead/Write Cycle DelayData Access TimeData Disable TimeIOW# Strobe WidthData Setup TimeData Hold Time

Delay From IOW# To Output

Delay To Set Interrupt From MODEM InputDelay To Reset Interrupt From IOR#Delay From Stop To Set InterruptDelay From IOR# To Reset InterruptDelay From Stop To Interrupt

Delay From Initial INT Reset To Transmit StartDelay From Stop To Reset RXRDYDelay From IOR# To Set RXRDYDelay From IOW# To Reset TXRDYDelay From Center of Start To Set TXRDYReset Pulse WidthBaud Rate DivisorBaud Clock

401

216-1

8040205

504040145241458

401

216-1

5105030

3525

025155

4035351404024140408

LIMITS3.3V

MIN MAX63

002530

2515

LIMITS5.0V

MIN MAX21

UNITnsMHznsnsnsnsnsnsnsnsnsnsnsnsnsBclknsnsBclkBclknsnsBclkns-Hz

100 pF load100 pF load100 pF load100 pF loadCONDITIONS

16X of data rate

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REV. 4.2.0áç

FIGURE 8. CLOCK TIMING

CLKEXTERNALCLOCKOSCCLK ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

FIGURE 9. MODEM INPUT/OUTPUT TIMINGIOW#IOWActiveTWDORTS#DTR#Change of stateChange of stateCD#CTS#DSR#TMODINTChange of stateChange of stateTMODActiveTRSIActiveActiveIOR#IORActiveActiveActiveTMODRI#Change of state27

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2.97V TO 5.5V UART WITH 16-BYTE FIFOFIGURE 10. DATA BUS READ TIMING

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REV. 4.2.0A0-A2TASCS2#ValidAddressTAHTCSTDYTASValidAddressTAHTCSIOR#TRDTRDTRDVD0-D7ValidDataTDDTRDVValidDataTDDFIGURE 11. DATA BUS WRITE TIMING

A0-A2TASCS2#ValidAddressTAHTCSTDYTASValidAddressTAHTCSIOW#TWRTWRTDSD0-D7ValidDataTDHTDSValidDataTDH28

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REV. 4.2.0áç

ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

FIGURE 12. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE]

RXStartBitStopBitTSSR1 Bytein RHRTSSRD0:D7D0:D7TSSR1 Bytein RHRTSSRD0:D7TSSR1 Bytein RHRTSSRINTRXRDY(ISR bit-5)ActiveDataReadyTRRActiveDataReadyTRRActiveDataReadyTRRIOR#(Reading dataout of RHR)RXNFMFIGURE 13. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE]

TX(Unloading)StartBitIER[1]enabledStopBitIER[1]enabledD0:D7D0:D7D0:D7IER[1]enabledINT cleared*INT cleared*INT cleared*INT*TSRTTSRTTSRTTXRDY(ISR bit-4)TWTTWTTWTIOW#(Loading datainto THR)*INT is cleared when the ISR is read and IER[1] is disabled.TXNonFIFO29

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

áç

REV. 4.2.0FIGURE 14. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED]

StartBitRXSD0:D7StopBitSD0:D7TD0:D7TSSISD0:D7TSD0:D7TSD0:D7TSD0:D7TRX FIFO dropsbelow RXTrigger LevelINTFirst Byte isReceived inRX FIFOTSSRRX FIFO fills up to RXTrigger Level or RX DataTimeoutFIFOEmptiesRXRDY(ISR bit-5)TRRITRRIOR#(Reading data outof RX FIFO)RXINTDMA#FIGURE 15. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED]

StartBitStopBitSD0:D7TRXSD0:D7D0:D7TSSISD0:D7TSD0:D7TSD0:D7TSD0:D7TRX FIFO dropsbelow RXTrigger LevelINTRX FIFO fills up to RXTrigger Level or RX DataTimeoutRXRDY(ISR bit-5)TRRITRRTSSRFIFOEmptiesIOR#(Reading data outof RX FIFO)RXFIFODMA30

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REV. 4.2.0áç

ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

FIGURE 16. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED]

StartBitStopBitLast Data ByteTransmittedSD0:D7TSD0:D7TTSITSD0:D7TSD0:D7TINT Cleared*TSRTSD0:D7TTX FIFOEmptyTXSD0:D7TINT*TX FIFO dropsbelow trigger levelTX FIFOEmptyTX FIFO above triggerlevel and IER[1] enabled.TXRDY(ISR bit-4)Data inTX FIFOTWTIOW#(Loading datainto FIFO)*INT is cleared when the ISR is read and IER[1] is disabled.TXDMA#FIGURE 17. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED]

StartBitStopBitLast Data ByteTransmittedD0:D7SD0:D7TSD0:D7TSD0:D7TSD0:D7TINT cleared*TXSD0:D7TSD0:D7TTSRTTSIINT*TX FIFO above triggerlevel and IER[1] enabled.TX FIFO dropsbelow trigger levelTXRDY(ISR bit-4)TX FIFOFullTWTAt least 1empty locationin FIFOIOW#(Loading datainto FIFO)*INT cleared when the ISR is read and IER[1] is disabled.TXDMA31

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

áç

REV. 4.2.0PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)DD136253724D1D48131BA2e12CASeatingPlaneαA1LNote: The control dimension is the millimeter columnINCHES

SYMBOL

AA1A2BCDD1eLα

MIN0.0390.0020.0370.0070.0040.3460.272

MAX0.0470.0060.0410.0110.0080.3620.280

MILLIMETERSMIN1.000.050.950.170.098.806.90

MAX1.200.151.050.270.209.207.10

0.020 BSC0.0180°

0.0307°

0.50 BSC0.450°

0.757°

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REV. 4.2.0áç

PACKAGE DIMENSIONS (28 PIN PDIP) ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

Note: The control dimension is the inch columnINCHES

SYMBOL

AA1A2BB1CDEE1eeAeBLα

MIN0.1600.0150.1250.0140.0300.0081.3800.6000.485

MAX0.2500.0700.1950.0240.0700.0141.5650.6250.580

MILLIMETERSMIN4.060.383.180.360.760.2035.0515.2412.32

MAX6.351.784.950.561.780.3839.7515.8814.73

0.100 BSC0.600 BSC0.6000.1150°

0.7000.20015°

2. BSC15.24 BSC15.242.920°

17.785.0815°

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ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

áç

REV. 4.2.0PACKAGE DIMENSIONS (28 PIN PLCC)Note: The control dimension is the inch columnINCHES

SYMBOL

AA1A2BB1CDD1D2D3eH1H2R

MIN0.1650.0900.0200.0130.0260.0080.4850.4500.390

MAX0.1800.120-0.0210.0320.0130.4950.4560.430

MILLIMETERSMIN4.192.290.510.330.660.1912.3211.439.91

MAX4.573.05-0.530.810.3212.5711.5810.92

7.62 typ.1.27 BSC1.071.070.

1.421.221.14

0.300 typ.0.050 BSC0.0420.0420.025

0.0560.0480.045

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REV. 4.2.0áç

ST16C1550/51

2.97V TO 5.5V UART WITH 16-BYTE FIFO

REVISION HISTORYDATE

January 2003

REVISIONRev 4.0.0

DESCRIPTION

Changed to standard style format. Clarified that the TX interrupt is not MS Windows compatible. Clarified timing diagrams. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and timing symbols. Added TAH, TCS and OSC. Updated Ordering Information.

Added Status Column to Ordering Information.

Clarified compatibility to industry standard 16550 and MS Windows standard serial port driver in General Description. Removed Auto RTS flow control from MCR bit-1 description since that feature is not available in this device.

April 2003September 2003October 2003

Rev 4.0.1Rev 4.1.0Rev 4.2.0

NOTICEEXAR Corporation reserves the right to make changes to the products contained in this publication in order toimprove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of anycircuits described herein, conveys no license under any patent or other right, and makes no representation thatthe circuits are free of patent infringement. Charts and schedules contained here in are only for illustrationpurposes and may vary depending upon a user’s specific application. While the information in this publicationhas been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where thefailure or malfunction of the product can reasonably be expected to cause failure of the life support system or tosignificantly affect its safety or effectiveness. Products are not authorized for use in such applications unlessEXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage hasbeen minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequatelyprotected under the circumstances. Copyright 2003 EXAR CorporationDatasheet October 2003.

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

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ST16C1550/51

REV. 4.2.0 TABLE OF CONTENTSáç

2.97V TO 5.5V UART WITH 16-BYTE FIFO

GENERAL DESCRIPTION.................................................................................................1

FEATURES.....................................................................................................................................................1APPLICATIONS................................................................................................................................................1FIGURE 1. BLOCK DIAGRAM.............................................................................................................................................................1FIGURE 2. ST16C1550 PINOUTS.....................................................................................................................................................2FIGURE 3. ST16C1551 PINOUTS.....................................................................................................................................................3ORDERING INFORMATION.................................................................................................................................4PIN DESCRIPTIONS .........................................................................................................5

DATA BUS INTERFACE.............................................................................................................................................5MODEM OR SERIAL I/O INTERFACE........................................................................................................................5ANCILLARY SIGNALS................................................................................................................................................6

1.0 PRODUCT DESCRIPTION .....................................................................................................................7

Enhanced Features.....................................................................................................................................................7.....................................................................................................................................................................................7Data Rate....................................................................................................................................................................7

2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................8

2.1 INTERNAL REGISTERS ................................................................................................................................... 82.2 DMA MODE ....................................................................................................................................................... 82.3 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK ......................................................................................... 8

TABLE 1: TXRDY AND RXRDY BITS IN FIFO AND DMA MODE........................................................................................................82.4 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................. 9

FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS.................................................................................................................................92.5 TRANSMITTER ............................................................................................................................................... 10

2.5.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 102.5.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................. 10TABLE 2: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK......................................................................102.5.3 TRANSMITTER OPERATION IN FIFO MODE........................................................................................................... 11

2.6 RECEIVER ...................................................................................................................................................... 11

2.6.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY............................................................................................ 11FIGURE 5. TRANSMITTER OPERATION IN NON-FIFO MODE..............................................................................................................112.7 SPECIAL (ENHANCED FEATURE) MODE .................................................................................................... 12

2.7.1 SOFT RESET.............................................................................................................................................................. 122.7.2 POWER DOWN MODE............................................................................................................................................... 122.7.3 TXRDY AND RXRDY BITS......................................................................................................................................... 12

2.8 INTERNAL LOOPBACK ................................................................................................................................ 12

FIGURE 6. RECEIVER OPERATION IN NON-FIFO MODE....................................................................................................................12FIGURE 7. INTERNAL LOOPBACK.....................................................................................................................................................133.0 UART INTERNAL REGISTERS ...........................................................................................................14

TABLE 3: ST16C155X UART INTERNAL REGISTERS...............................................................................................................14TABLE 4: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1.........................................1.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................16

4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 1.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 1.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 16

4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION............................................................................. 1.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 16

4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 17

4.4.1 INTERRUPT GENERATION:...................................................................................................................................... 174.4.2 INTERRUPT CLEARING:........................................................................................................................................... 17

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 18

TABLE 5: INTERRUPT SOURCE AND PRIORITY LEVEL.......................................................................................................................184.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 19

TABLE 6: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION..............................................................................................19TABLE 7: PARITY SELECTION..........................................................................................................................................................204.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 214.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 224.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 234.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 23

TABLE 8: UART RESET CONDITIONS........................................................................................................................................24I

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2.97V TO 5.5V UART WITH 16-BYTE FIFO

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ST16C1550/51

REV. 4.2.0 ABSOLUTE MAXIMUM RATINGS..................................................................................25

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%).................................................25ELECTRICAL CHARACTERISTICS................................................................................25

DC ELECTRICAL CHARACTERISTICS..............................................................................................................25AC ELECTRICAL CHARACTERISTICS..............................................................................................................26TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V......................26FIGURE 8. CLOCK TIMING...............................................................................................................................................................27FIGURE 9. MODEM INPUT/OUTPUT TIMING......................................................................................................................................27FIGURE 10. DATA BUS READ TIMING..............................................................................................................................................28FIGURE 11. DATA BUS WRITE TIMING............................................................................................................................................28FIGURE 12. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE]............................................................................................29FIGURE 13. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE]..........................................................................................29FIGURE 14. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED]..........................................................................30FIGURE 15. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED]...........................................................................30FIGURE 16. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED]..............................................................31FIGURE 17. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED]...............................................................31PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)....................................................................................32PACKAGE DIMENSIONS (28 PIN PDIP)..........................................................................................................33PACKAGE DIMENSIONS (28 PIN PLCC).........................................................................................................34REVISION HISTORY......................................................................................................................................35TABLE OF CONTENTS ............................................................................................................III

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