GL830 Datasheet _101

 Genesys Logic, Inc. GL830 USB 2.0 to SATA Bridge Controller Datasheet Revision 1.01 Jul. 17, 2007 GL830 USB2.0 to SATA Bridge Controller Copyright: Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Disclaimer: ALL MATERIALS ARE PROVIDED \"AS IS\" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registrated trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 13-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com ©2007 Genesys Logic Inc. - All rights reserved. Page 2 GL830 USB2.0 to SATA Bridge Controller Revision History Revision 1.00 1.01 Date 06/14/2007 First Formal Release 7/17/2007 Description Add 48 and 128pin description ©2007 Genesys Logic Inc. - All rights reserved. Page 3 GL830 USB2.0 to SATA Bridge Controller TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION...................................................8 CHAPTER 2 FEATURES..............................................................................9 CHAPTER 3 PIN ASSIGNMENT..............................................................10 3.1 PINOUTS....................................................................................................10 3.2 PIN LIST....................................................................................................13 3.3 PIN DESCRIPTIONS...................................................................................15 CHAPTER 4 BLOCK DIAGRAM..............................................................22 CHAPTER 5 FUNCTION DESCRIPTION...............................................23 5.1 UTM.........................................................................................................23 5.2 SIE............................................................................................................23 5.3 EP0/EP3 FIFO AND BULK BUFFER........................................................23 5.4 OPERATION REGISTER.............................................................................23 5.5 SPI INTERFACE........................................................................................23 5.6 PHY LAYER.............................................................................................23 5.7 LINK LAYER.............................................................................................23 5.8 TRANSPORT LAYER..................................................................................23 5.9 APPLICATION LAYER...............................................................................23 CHAPTER 6 ELECTRICAL CHARACTERISTICS...............................24 6.1 ABSOLUTE MAXIMUM RATINGS..............................................................24 6.2 TEMPERATURE CONDITIONS...................................................................24 6.3 DC CHARACTERISTICS............................................................................24 6.3.1 I/O Type digital pins.......................................................................24 6.3.2 USB Interface DC Characteristics................................................25 6.3.3 SATA Interface DC Characteristics.............................................25 6.3.4 Reference Clock Input Requirement............................................25 6.3.5 Reference Resistor Requirement...................................................25 6.4 AC CHARACTERISTICS............................................................................25 6.4.1 USB Interface AC Characteristics................................................25 ©2007 Genesys Logic Inc. - All rights reserved. Page 4 GL830 USB2.0 to SATA Bridge Controller 6.4.2 SATA Interface AC Characteristics.............................................25 CHAPTER 7 PACKAGE DIMENSION.....................................................26 CHAPTER 8 ORDERING INFORMATION............................................29 ©2007 Genesys Logic Inc. - All rights reserved. Page 5 GL830 USB2.0 to SATA Bridge Controller LIST OF FIGURES FIGURE 3.1 - 48 PIN LQFP PINOUT DIAGRAM..................................................................10 FIGURE 3.2 - PIN LQFP PINOUT DIAGRAM..................................................................11 FIGURE 3.3 - 128 PIN LQFP PINOUT DIAGRAM...............................................................12 FIGURE 4.1 - BLOCK DIAGRAM.........................................................................................22 FIGURE 7.1 – GL830 48 PIN LQFP PACKAGE..................................................................26 FIGURE 7.2 - GL830 PIN LQFP PACKAGE...................................................................27 FIGURE 7.3 - GL830 128 PIN LQFP PACKAGE.................................................................28 ©2007 Genesys Logic Inc. - All rights reserved. Page 6 GL830 USB2.0 to SATA Bridge Controller LIST OF TABLES TABLE 3.1 – 48 PIN LIST....................................................................................................13 TABLE 3.2 – PIN LIST....................................................................................................13 TABLE 3.3 – 128 PIN LIST..................................................................................................14 TABLE 3.4 – 48 PIN DESCRIPTIONS....................................................................................15 TABLE 3.5 – PIN DESCRIPTIONS....................................................................................16 TABLE 3.6 – 128 PIN DESCRIPTIONS..................................................................................18 TABLE 6.1 - MAXIMUM RATINGS......................................................................................24 TABLE 6.2 - TEMPERATURE CONDITIONS.........................................................................24 TABLE 6.3 - I/O TYPE DIGITAL PINS..................................................................................24 TABLE 6.6 - REFERENCE CLOCK INPUT REQUIREMENT..................................................25 TABLE 6.7 - REFERENCE RESISTOR REQUIREMENT.........................................................25 TABLE 8.1 - ORDERING INFORMATION.............................................................................29 ©2007 Genesys Logic Inc. - All rights reserved. Page 7 GL830 USB2.0 to SATA Bridge Controller CHAPTER 1 GENERAL DESCRIPTION The GL830 is a highly-compatible, low cost USB 2.0 to SATA bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver/receiver and Serial ATA PHY. As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and Serial ATA specification rev. 2.6. There are totally 4 endpoints in the GL830 controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL830 can support not only plug and play but also Windows Vista/ XP/ 2000/ ME default driver. The GL830 uses 25MHz crystal and slew-rate controlled pads to reduce the EMI issue. With -pin LQFP (7mmX7mm) package, the GL830 is the best cost/ performance solution to fit different situations in the USB 2.0 high speed storage class applications such as SATA HDD and ODD. ©2007 Genesys Logic Inc. - All rights reserved. Page 8 GL830 USB2.0 to SATA Bridge Controller CHAPTER 2 FEATURES · Complies with Universal Serial Bus specification rev. 2.0. · Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) · Operating system supported: Win Vista/ Win XP / 2000 / Me / 98 / 98SE; Mac OS 9.X / X. · Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) transceiver and Serial Interface Engine (SIE). · Support 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3). · / 512 bytes Data Payload for full / high speed Bulk Endpoint. · Complies with Serial ATA specification rev. 2.6. · Support SATA hot-plug · Support Spread Spectrum Clocking to reduce EMI · Support Partial/Slumber power management · Provide adjustable TX signal amplitude and pre-emphasis level · Provide specified OOB signal detection and transmission · Embedded Turbo 8051. · ROM size: 12k words; RAM size: 1280 bytes. (Bulk Buffer: 512 words, MC RAM: 256 bytes) · Supports Power Down mode and USB suspend indicator. · Supports USB 2.0 TEST mode features. · Supports 4 PIO and 4GPIO for programmable AP. · Supports device power control for power on/off when running suspend mode. · Provides LED indicator for Full Speed and High Speed . · using 25 MHz external clock to provide better EMI. · 3.3V power input; 5V tolerance pad. · Supports Wakeup ability. · Embedded Regulator (3.3V to 1.8V). · Embedded Regulator (5V to 3.3V). · Provides SPI interface for Finger Print (only for pin package). · Available in 48//128-pin LQFP. ©2007 Genesys Logic Inc. - All rights reserved. Page 9 GL830 USB2.0 to SATA Bridge Controller CHAPTER 3 PIN ASSIGNMENT 3.1 Pinouts AGNDAVDDCVDDCVDDGNDVDDGNDVDD3635343332313029282726RTERMPLLVDDPLLVSSTXVSSTXVDD3738394041424344474825DMDPX1X224232221201918171615AGNDRREFAVDDNCGPIO1NCPIO2GPIO2NCV5VDDGND

TXPTXNRXNRXPRXVDDRXVSSCVDDLQFP -4814131011PIO1HRST_PIO3GPIO0GPIO3CVDDTESTPIO0 Figure 3.1 - 48 Pin LQFP Pinout Diagram ©2007 Genesys Logic Inc. - All rights reserved. CVDDGNDVDDGND121234567 Page 10 GL830 USB2.0 to SATA Bridge Controller 47PLLVDDPLLVSSRXPEXTRXNEXTTXNEXT44434138363332313029282726NCNCGPIO1NCNCPIO2NCGPIO2NCV5VDDGNDCVDDNCNCNC

495051525355565758596061626312361214TXPEXTTXVSSTXVDDTXPTXNRXNRXPRXVDDRXVSSCVDDGNDGL830LQFP -252423222120191817 ©2007 Genesys Logic Inc. - All rights reserved. Page 11 GL830 USB2.0 to SATA Bridge Controller NCNCNCNCNCNCNCPLLVDDPLLVDDPLLVSSRXPEXTRXNEXTTXNEXTTXPEXTTXVSSTXVDD

TXPTXNRXNRXPRXVDDRXVSSCVDDGNDNCROM_A8ROM_A7ROM_A9ROM_A6ROM_A10ARESET_SPDSEL

9799100101102103104105106107108109110111112113114115116117118119120121122123124125126127128GL830LQFP -12863626160595857565553525150494847444342414039383736353433GPIO4PHYRDYDMACK_GPIO1IORDYT_ROMDIOR_PIO2DIOW_GPIO2DMARQROM_D5V5VDDVDDMODE1GNDCVDDDD15ROM_D2DD0

ROM_D6DD14ROM_D1DD1

ROM_D7DD13ROM_D0DD2

ROM_A0PIO1PIO0

Figure 3.3 - 128 Pin LQFP Pinout Diagram ©2007 Genesys Logic Inc. - All rights reserved. Page 12 GL830 USB2.0 to SATA Bridge Controller 3.2 Pin List Table 3.1 – 48 Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 2 3 4 5 6 7 8 9 10 11 12 GND GPIO0 GPIO3 PIO3 HRST_ CVDD VDD GND TEST PIO0 PIO1 CVDD P B B B I P P P I B B P 13 14 15 16 17 18 19 20 21 22 23 24 GND VDD V5 NC GPIO2 PIO2 NC GPIO1 NC AVDD RREF AGND P P P - B B - B - P A P 25 26 27 28 29 30 31 32 33 34 35 36 DM DP AVDD AGND CVDD VDD GND VDD X2 X1 CVDD GND B B P P P P P P B I P P 37 38 39 40 41 42 43 44 45 46 47 48 RTERM PLLVDD PLLVSS TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD A P P P P O O I I P P P Table 3.2 – Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 2 3 4 5 6 7 8 9 10 11 12 13 GPIO0 GPIO3 PIO3 NC HRST_ NC NC CVDD VDD MODE GND TEST NC B B B - I - - P P I P I - 17 18 19 20 21 22 23 24 25 26 27 28 29 NC NC NC CVDD GND VDD V5 NC GPIO2 NC PIO2 NC NC - - - P P P P - B - B - - 33 34 35 36 37 38 39 40 41 42 43 44 45 AVDD RREF AGND DM DP AVDD3 AGND3 CVDD VDD GND VDD X2 X1 P A P B B P P P P P P B I 49 50 51 52 53 55 56 57 58 59 60 61 PLLVDD PLLVSS RXPEXT RXNEXT TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD P P I I O O P P O O I I P ©2007 Genesys Logic Inc. - All rights reserved. Page 13 GL830 USB2.0 to SATA Bridge Controller 14 15 16 NC PIO0 PIO1 - B B 30 31 32 GPIO1 NC NC B - - 46 47 48 CVDD GND RTERM P P A 62 63 RXVSS CVDD GND P P P Table 3.3 – 128 Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GPIO0 GPIO3 PIO4 PIO3 ROM_A5 DD7 ROM_A11 DD8 HRST_ DD6 ROM_A4 DD9 ROM_A12 DD5 ROM_A3 CVDD CVDD VDD MOD0 GND DD10 ROM_A13 TEST TXD RXD B B B B O B O B I B O B O B O P P P I P B O I O B 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 55 56 57 PIO0 PIO1 ROM_A0 DD2 ROM_D0 DD13 ROM_D7 DD1 ROM_D1 DD14 ROM_D6 DD0 ROM_D2 DD15 CVDD GND MODE1 VDD VDD V5 ROM_D5 DMARQ GPIO2 DIOW_ PIO2 B B O B B B B B B B B B B B P P I P P I B B B B B 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 AINTRQ AVDD AVDD RREF AGND AGND DM DP AVDD AGND GND GND CVDD DA1 DA0 NC DA2 ROM_D3 CS0_ ROM_D4 CS1_ GND VDD VDD GND B P P 97 98 99 NC NC NC NC NC NC NC PLLVDD PLLVDD PLLVSS RXPEXT RXNEXT TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD GND NC - - - - - - - P P P I I O O P P O O I I P P P P - A 100 P P B B P P P P P B B - B B B B B P P P P 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 ©2007 Genesys Logic Inc. - All rights reserved. Page 14 GL830 USB2.0 to SATA Bridge Controller 26 27 28 29 30 31 32 DD4 ROM_A2 DD11 ROM_A14 DD3 ROM_A1 DD12 B O B O B O B 58 59 60 61 62 63 DIOR_ T_ROM IORDY GPIO1 DMACK_ PHYRDY GPIO4 B I B B B O B 90 91 92 93 94 95 96 GND VDD X2 X1 VDD GND RTERM P P B I P P 122 123 124 125 ROM_A8 ROM_A7 ROM_A9 ROM_A6 O O O O O B I 126 ROM_A10 127 ARESET_ SPDSEL A 128 3.3 Pin Descriptions Table 3.4 – 48 Pin Descriptions USB Interface Pin Name RREF DM DP AVDD AGND Pin# 23 25 26 22,27 24,28 Type A B B P P Reference resistor HS D- HS D+ USB Analog 3.3V power USB Analog Ground Description SATA Interface Pin Name RTERM PLLVDD PLLVSS TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS Pin# 37 38 39 40 41 42 43 44 45 46 47 Type A P P P P O O I I P P Reference resistor 1.8V Power Supplies for internal PLL Ground for internal PLL 1.8V Power Supplies for transceiver part Ground for transceiver part SATA Differential Transmit TX+ SATA Differential Transmit TX- SATA Differential Receive RX- SATA Differential Receive RX+ 1.8V Power Supplies for receiver part Ground for receiver part Description Digital Power and Ground Pin Name Pin# Type Description ©2007 Genesys Logic Inc. - All rights reserved. Page 15 GL830 USB2.0 to SATA Bridge Controller 6,12,29, 35,48 7,14 30, 32 1,8,13, 31,36 15 CVDD P 1.8V Digital Power VDD P 3.3V Digital Power GND V5 P p Digital Ground 5V Power Input Miscellaneous Interface Pin Name TEST X2 X1 HRST_ GPIO0~3 PIO0~3 NC Pin# 9 33 34 5 2,20,17,3 10,11,18, 4 16,19,21 Type I (pd) Test Mode Input B I Crystal Output Crystal Input Description I (pu) Reset Pin B General Purpose I/O #0~#3 (pu) B Programmable I/O #0~#3 (pd) - No connection Table 3.5 – Pin Descriptions USB Interface Pin Name RREF DM DP AVDD AGND Pin# 34 36 37 33,38 35,39 Type A B B P P Reference resistor HS D- HS D+ USB Analog 3.3V power USB Analog Ground Description SATA Interface Pin Name RTERM PLLVDD PLLVSS RXPEXT RXNEXT Pin# 48 49 50 51 52 Type A P P I I Reference resistor Description 1.8V Power Supplies for internal PLL Ground for internal PLL eSATA Differential Receive RX+ eSATA Differential Receive RX- ©2007 Genesys Logic Inc. - All rights reserved. Page 16 GL830 USB2.0 to SATA Bridge Controller TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS 53 55 56 57 58 59 60 61 62 O O P P O O I I P P eSATA Differential Transmit TX- eSATA Differential Transmit TX+ 1.8V Power Supplies for transceiver part Ground for transceiver part SATA Differential Transmit TX+ SATA Differential Transmit TX- SATA Differential Receive RX- SATA Differential Receive RX+ 1.8V Power Supplies for receiver part Ground for receiver part Digital Power and Ground Pin Name CVDD Pin# 8,20,40, 46,63 9,22,41, 43 11,21,42, 47, 23 Type P 1.8V Digital Power Description VDD P 3.3V Digital Power GND V5 P p Digital Ground 5V Power Input Miscellaneous Interface Pin Name TEST X2 X1 HRST_ MODE GPIO0~3 PIO0~3 Pin# 12 44 45 5 10 1,30,25,2 15,16,27,3 4,6,7,13, 14,17,18, 19,24,26,28,29,31,32 Type I (pd) Test Mode Input B I Crystal Output Crystal Input Description I (pu) Reset Pin I (pd) Mode Select (1=> USB to SATA; 0=> eSATA to SATA) B General Purpose I/O #0~#3 (pu) B Programmable I/O #0~#3 (pd) - No connection NC ©2007 Genesys Logic Inc. - All rights reserved. Page 17 GL830 USB2.0 to SATA Bridge Controller Table 3.6 – 128 Pin Descriptions USB Interface Pin Name RREF DM DP AVDD AGND Pin# 68 71 72 66,67,73 69,70,74 Type A B B P P Reference resistor HS D- HS D+ USB Analog 3.3V power USB Analog Ground Description SATA Interface Pin Name RTERM PLLVDD PLLVSS RXPEXT RXNEXT TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS Pin# 96 104,105 106 107 108 109 110 111 112 113 114 115 116 117 118 Type A P P I I O O P P O O I I P P Reference resistor 1.8V Power Supplies for internal PLL Ground for internal PLL eSATA Differential Receive RX+ eSATA Differential Receive RX- eSATA Differential Transmit TX- eSATA Differential Transmit TX+ 1.8V Power Supplies for transceiver part Ground for transceiver part SATA Differential Transmit TX+ SATA Differential Transmit TX- SATA Differential Receive RX- SATA Differential Receive RX+ 1.8V Power Supplies for receiver part Ground for receiver part Description Digital Power and Ground Pin Name CVDD VDD Pin# 16,17,47,77,119 18,50,51 87,88,91, 94 20,48,75, 76,86,,90,95, 120 Type P P 1.8V Digital Power 3.3V Digital Power Description GND P Digital Ground ©2007 Genesys Logic Inc. - All rights reserved. Page 18 GL830 USB2.0 to SATA Bridge Controller V5 52 p 5V Power Input ATA/ ATAPI Interface (Host mode) Pin Name Pin# 44,40,36,30,26,14,10,6,8,12,21,28,32,38,42,46 127 85, 83 79,78,81 65 62 60 58 56 Type Description DD0~15 B IDE Data Bus ARESET_ CS1_, CS0_ DA0~2 INTRQ DMACK_ IORDY DIOR_ DIOW_ DMARQ I Device Reset (pu) I (pu) Chip Select #1,#0 I IDE Address #2,#1,#0 (pd) O IDE interrupt input I IDE Acknowledge (pu) O IDE Ready I IDE read signal (pu) I IDE write signal (pu) O IDE request ATA/ ATAPI Interface (Device mode) Pin Name Pin# 44,40,36,30,26,14,10,6,8,12,21,28,32,38,42,46 127 85, 83 79,78,81 65 62 60 58 56 Type Description DD0~15 B IDE Data Bus ARESET_ CS1_, CS0_ DA0~2 INTRQ DMACK_ IORDY DIOR_ DIOW_ DMARQ O O O Device Reset Chip Select #1,#0 IDE Address #2,#1,#0 I IDE interrupt input (pd) O IDE Acknowledge I IDE Ready (pu) O O IDE read signal IDE write signal I IDE request (pd) Page 19 ©2007 Genesys Logic Inc. - All rights reserved. GL830 USB2.0 to SATA Bridge Controller Miscellaneous Interface Pin Name TEST X2 X1 HRST_ Pin# 23 92 93 9 Type I (pd) Test Mode Input B I Crystal Output Crystal Input Description I (pu) Reset Pin MODE0,1 GPIO0~4 PIO0~4 TXD RXD SPDSEL PHYRDY T_ROM Mode Select 00=> USB to SATA; 10=> eSATA to SATA; I 19,49 01=> USB to PATA; 11=> SATA to PATA (pd) When MODE0,1=11, PIO1=0 is device mode. When MODE0,1=11, PIO1=1 is host mode. 1,61,55,2,B General Purpose I/O #0~#4 (pu) 33,34,57,B Programmable I/O #0~#4 4,3 (pd) O 24 8051 UART TXD (pu) B 25 8051 UART RXD (pu) B 0 => force in 1.5G; 1 => negotiate interface speed with attached 128 (pd) device (1.5G or 3G) 63 59 O SATA PHY ready I (pd) 0 => Internal ROM; 1 => External ROM 35,31,27,15,11,5, 125,123, ROM_A0~14 122,124, 126,7,13, 22,29 37,41,45,ROM_D0~7 82,84,53,43,39 80,97,98,99,100, NC 101,102, 103 Notation: Type O ROM Address #0~#14 B ROM Data #0~#7 (pd) - No connection O I B B/I B/O P A Output Input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Page 20 ©2007 Genesys Logic Inc. - All rights reserved. GL830 USB2.0 to SATA Bridge Controller SO pu pd odpu Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up ©2007 Genesys Logic Inc. - All rights reserved. Page 21 GL830 USB2.0 to SATA Bridge Controller CHAPTER 4 BLOCK DIAGRAM GPIOPATAApplication LayerSPITransport LayerBulk BufferEP0/3 FIFOControllerOperationRegisterLink LayerSIE8051 CorePHY LayerUTMROMRAMeSATASATAUSB Figure 4.1 - Block Diagram ©2007 Genesys Logic Inc. - All rights reserved. Page 22 GL830 USB2.0 to SATA Bridge Controller CHAPTER 5 FUNCTION DESCRIPTION 5.1 UTM The USB 2.0 Transceiver Macrocell, it’s the analog circuitry that handles the low level USB protocol and signaling, and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic. 5.2 SIE The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing and state machine logic to handle USB packets and transactions. 5.3 EP0/EP3 FIFO and Bulk Buffer Endpoint 0/3 FIFO: The Control and Interrupt FIFO. It is composed of TX03FIFO and RX03FIFO, with -byte FIFO each, and it is used for endpoint 0/3 data transfer. Bulk Buffer: It is constructed in interleaved architecture and composed by two data buffers which is used to store data transferred between USB host and IDE device. 5.4 Operation Register It is a register space to store status information and to control the functions of GL830 by 8051. 5.5 SPI Interface The Serial Peripheral Interface is a serial, synchronous communication protocol. It is compatible with Motorola’s SPI specifications. 5.6 PHY Layer It has elastic buffer and supports receiver detection, data serialization and de-serialization. 5.7 Link Layer The Link layer transmits and receives frames, transmits primitives based on control signals from the Transport layer, and receives primitives from the Phy layer which are converted to control signals to the Transport layer. 5.8 Transport Layer The Transport layer constructs Frame Information Structures for transmission and decomposes received Frame Information Structure 5.9 Application Layer The Application Layer translates the ATA operation onto internal protocols. ©2007 Genesys Logic Inc. - All rights reserved. Page 23 GL830 USB2.0 to SATA Bridge Controller CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings Table 6.1 - Maximum Ratings Symbol VIO Parameter Digital I/O pad power supply voltage Min. 3.0 1.62 3.0 1.62 4000 0 Typ. 3.3 1.8 3.3 1.8 Max. 3.6 1.98 3.6 1.98 100 Unit V V V V V oVcore Digital power supply voltage VAUSB Analog power supply voltage for USB PHY VASATA Analog power supply voltage for SATA PHY VESD TA Static discharge voltage Ambient Temperature C 6.2 Temperature Conditions Table 6.2 - Temperature Conditions Item Storage Temperature Operating Temperature Value -50oC ~ 150 oC 0 oC ~ 70 oC 6.3 DC Characteristics 6.3.1 I/O Type digital pins Table 6.3 - I/O Type digital pins Parameter Current sink @ VOL = 0.4V Current output @ VOH = 2.4V (TTL high) Falling slew rate at 30 pF loading capacitance Rising slew rate at 30 pF loading capacitance Schmitt trigger low to high threshold point Schmitt trigger low to high threshold point Pad internal pull up resister Pad internal pull down resister Min. 10.58 14.74 0.56 0.58 1.4 1.4 37.87K 29.85K Typ. 14.21 27.46 0.91 0.91 1.5 1.5 .7K 59.45K Max. 16.87 43.0 1.28 1.72 1.6 1.6 108.11K 134.26K Unit mA mA V/ns V/ns V V Ohms Ohms ©2007 Genesys Logic Inc. - All rights reserved. Page 24 GL830 USB2.0 to SATA Bridge Controller 6.3.2 USB Interface DC Characteristics The GL830 conforms to DC characteristics for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information. 6.3.3 SATA Interface DC Characteristics The GL830 conforms to DC characteristics for Serial ATA specification rev. 2.6. Please refer to this specification for more information. 6.3.4 Reference Clock Input Requirement Table 6.6 - Reference Clock Input Requirement Parameter X1 crystal frequency X1 cycle time Min. Typ. 25 40 Max. Unit MHz ns 6.3.5 Reference Resistor Requirement Table 6.7 - Reference Resistor Requirement Parameter USB Reference Resistor SATA Reference Resistor Min. Typ. 680 5.1K Max. Unit Ohms Ohms 6.4 AC Characteristics 6.4.1 USB Interface AC Characteristics The GL830 conforms to all timing diagrams and specifications for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information. 6.4.2 SATA Interface AC Characteristics The GL830 conforms to all timing diagrams and specifications for Serial ATA specification rev. 2.6. Please refer to this specification for more information. ©2007 Genesys Logic Inc. - All rights reserved. Page 25 GL830 USB2.0 to SATA Bridge Controller CHAPTER 7 PACKAGE DIMENSION ©2007 Genesys Logic Inc. - All rights reserved. Page 26 GL830 USB2.0 to SATA Bridge Controller ©2007 Genesys Logic Inc. - All rights reserved. Page 27 GL830 USB2.0 to SATA Bridge Controller DD1D2DAA20.05SA1969765InternalNo.AE1E2EGL830AAAAAAAGAAYWWXXXXXXXXDate CodeLot CodeGreenPackageBCodeNo.1281324Xeb33bbbHABDL14XaaaCABD-10-0dddMCABsDscCcccCSEATING PLANE0-2R1HR20.25mmGAGE PLANESL0-3NOTES :

1.DIMENSIONS D1 AND E1 DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE

DIMENSIONS INCLUDING MOLD MISMATCH.2.DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.

CONTROL DIMENSIONS ARE IN MILLIMETERS.

MILLIMETERINCHSYMBOL

MIN.NOM.MAX.MIN.NOM.MAX.0.063A1.600.0060.050.150.002A11.351.401.450.0530.0550.057A216.00 BASIC0.630 BASICD16.00 BASIC0.630 BASICE

14.00 BASIC0.551 BASICD1

14.00 BASIC0.551 BASICE1

12.40 BASICD20.488 BASIC12.40 BASICE20.488 BASIC0.080.003R10.080.200.0030.008R2-003.5703.57-1000-20111213111213-301112131112130.090.200.0040.008c

0.450.600.750.0180.0240.030L

1.00 REF0.039 REFL1

0.0080.20S0.230.0050.0060.0090.130.16b0.40 BASIC0.016 BASICeTOLERANCES OF FORM AND POSITION0.200.008aaa0.200.008bbbccc0.080.0030.003ddd0.07 Figure 7.3 - GL830 128 Pin LQFP Package ©2007 Genesys Logic Inc. - All rights reserved. Page 28 GL830 USB2.0 to SATA Bridge Controller CHAPTER 8 ORDERING INFORMATION Table 8.1 - Ordering Information Part Number GL830-MNGXX GL830-MSGXX GL830-MXGXX Package 48-pin LQFP -pin LQFP 128-pin LQFP Green Green Package Green Package Green Package Version XX XX XX Status Available Available Available ©2007 Genesys Logic Inc. - All rights reserved. Page 29